/*
* Atheros AR71xx SoC specific definitions
*
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
- * Parts of this file are based on Atheros' 2.6.15 BSP
+ * Parts of this file are based on Atheros 2.6.15 BSP
+ * Parts of this file are based on Atheros 2.6.31 BSP
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
#define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
#define AR91XX_WMAC_SIZE 0x30000
+#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
+#define AR933X_UART_SIZE 0x14
+#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+#define AR933X_WMAC_SIZE 0x20000
+
+#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+#define AR934X_WMAC_SIZE 0x20000
+
#define AR71XX_MEM_SIZE_MIN 0x0200000
#define AR71XX_MEM_SIZE_MAX 0x10000000
#define AR71XX_CPU_IRQ_BASE 0
#define AR71XX_MISC_IRQ_BASE 8
-#define AR71XX_MISC_IRQ_COUNT 8
-#define AR71XX_GPIO_IRQ_BASE 16
+#define AR71XX_MISC_IRQ_COUNT 32
+#define AR71XX_GPIO_IRQ_BASE 40
#define AR71XX_GPIO_IRQ_COUNT 32
-#define AR71XX_PCI_IRQ_BASE 48
+#define AR71XX_PCI_IRQ_BASE 72
#define AR71XX_PCI_IRQ_COUNT 8
-#define AR71XX_CPU_IRQ_PCI (AR71XX_CPU_IRQ_BASE + 2)
-#define AR71XX_CPU_IRQ_WMAC (AR71XX_CPU_IRQ_BASE + 2)
+#define AR71XX_CPU_IRQ_IP2 (AR71XX_CPU_IRQ_BASE + 2)
#define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3)
#define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4)
#define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5)
#define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5)
#define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6)
#define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7)
+#define AR71XX_MISC_IRQ_TIMER2 (AR71XX_MISC_IRQ_BASE + 8)
+#define AR71XX_MISC_IRQ_TIMER3 (AR71XX_MISC_IRQ_BASE + 9)
+#define AR71XX_MISC_IRQ_TIMER4 (AR71XX_MISC_IRQ_BASE + 10)
+#define AR71XX_MISC_IRQ_DDR_PERF (AR71XX_MISC_IRQ_BASE + 11)
+#define AR71XX_MISC_IRQ_ENET_LINK (AR71XX_MISC_IRQ_BASE + 12)
#define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x))
extern u32 ar71xx_ahb_freq;
extern u32 ar71xx_cpu_freq;
extern u32 ar71xx_ddr_freq;
+extern u32 ar71xx_ref_freq;
enum ar71xx_soc_type {
AR71XX_SOC_UNKNOWN,
AR71XX_SOC_AR7141,
AR71XX_SOC_AR7161,
AR71XX_SOC_AR7240,
+ AR71XX_SOC_AR7241,
+ AR71XX_SOC_AR7242,
AR71XX_SOC_AR9130,
- AR71XX_SOC_AR9132
+ AR71XX_SOC_AR9132,
+ AR71XX_SOC_AR9330,
+ AR71XX_SOC_AR9331,
+ AR71XX_SOC_AR9341,
+ AR71XX_SOC_AR9342,
+ AR71XX_SOC_AR9344,
};
+extern u32 ar71xx_soc_rev;
extern enum ar71xx_soc_type ar71xx_soc;
-enum ar71xx_mach_type {
- AR71XX_MACH_GENERIC = 0,
- AR71XX_MACH_AP81, /* Atheros AP81 */
- AR71XX_MACH_AP83, /* Atheros AP83 */
- AR71XX_MACH_AW_NR580, /* AzureWave AW-NR580 */
- AR71XX_MACH_DIR_825_B1, /* D-Link DIR-825 rev. B1 */
- AR71XX_MACH_RB_411, /* MikroTik RouterBOARD 411/411A/411AH */
- AR71XX_MACH_RB_411U, /* MikroTik RouterBOARD 411U */
- AR71XX_MACH_RB_433, /* MikroTik RouterBOARD 433/433AH */
- AR71XX_MACH_RB_433U, /* MikroTik RouterBOARD 433UAH */
- AR71XX_MACH_RB_450, /* MikroTik RouterBOARD 450 */
- AR71XX_MACH_RB_450G, /* MikroTik RouterBOARD 450G */
- AR71XX_MACH_RB_493, /* Mikrotik RouterBOARD 493/493AH */
- AR71XX_MACH_PB42, /* Atheros PB42 */
- AR71XX_MACH_PB44, /* Atheros PB44 */
- AR71XX_MACH_MZK_W04NU, /* Planex MZK-W04NU */
- AR71XX_MACH_MZK_W300NH, /* Planex MZK-W300NH */
- AR71XX_MACH_TEW_632BRP, /* TRENDnet TEW-632BRP */
- AR71XX_MACH_TL_WR741ND, /* TP-LINK TL-WR741ND */
- AR71XX_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */
- AR71XX_MACH_TL_WR1043ND,/* TP-LINK TL-WR1041ND */
- AR71XX_MACH_UBNT_LSSR71, /* Ubiquiti LS-SR71 */
- AR71XX_MACH_UBNT_LSX, /* Ubiquiti LSX */
- AR71XX_MACH_UBNT_RS, /* Ubiquiti RouterStation */
- AR71XX_MACH_UBNT_RSPRO, /* Ubiquiti RouterStation Pro */
- AR71XX_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */
- AR71XX_MACH_UBNT_ROCKET_M, /* Ubiquiti Rocket M */
- AR71XX_MACH_UBNT_NANO_M, /* Ubiquiti NanoStation M */
- AR71XX_MACH_WNR2000, /* NETGEAR WNR2000 */
- AR71XX_MACH_WNDR3700, /* NETGEAR WNDR3700 */
- AR71XX_MACH_WP543, /* Compex WP543 */
- AR71XX_MACH_WRT160NL, /* Linksys WRT160NL */
- AR71XX_MACH_WRT400N, /* Linksys WRT400N */
-};
-
-extern enum ar71xx_mach_type ar71xx_mach;
-
/*
* PLL block
*/
#define AR71XX_ETH1_PLL_SHIFT 19
#define AR724X_PLL_REG_CPU_CONFIG 0x00
+#define AR724X_PLL_REG_PCIE_CONFIG 0x18
#define AR724X_PLL_DIV_SHIFT 0
#define AR724X_PLL_DIV_MASK 0x3ff
#define AR724X_DDR_DIV_SHIFT 22
#define AR724X_DDR_DIV_MASK 0x3
+#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
+
#define AR91XX_PLL_REG_CPU_CONFIG 0x00
#define AR91XX_PLL_REG_ETH_CONFIG 0x04
#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
#define AR91XX_ETH0_PLL_SHIFT 20
#define AR91XX_ETH1_PLL_SHIFT 22
+#define AR933X_PLL_CPU_CONFIG_REG 0x00
+#define AR933X_PLL_CLOCK_CTRL_REG 0x08
+
+#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
+#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
+#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
+#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
+
+#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
+
+#define AR934X_PLL_REG_CPU_CONFIG 0x00
+#define AR934X_PLL_REG_DDR_CTRL_CLOCK 0x8
+
+#define AR934X_CPU_PLL_CFG_OUTDIV_MSB 21
+#define AR934X_CPU_PLL_CFG_OUTDIV_LSB 19
+#define AR934X_CPU_PLL_CFG_OUTDIV_MASK 0x00380000
+
+#define AR934X_CPU_PLL_CFG_OUTDIV_GET(x) \
+ (((x) & AR934X_CPU_PLL_CFG_OUTDIV_MASK) >> \
+ AR934X_CPU_PLL_CFG_OUTDIV_LSB)
+
+#define AR934X_DDR_PLL_CFG_OUTDIV_MSB 25
+#define AR934X_DDR_PLL_CFG_OUTDIV_LSB 23
+#define AR934X_DDR_PLL_CFG_OUTDIV_MASK 0x03800000
+
+#define AR934X_DDR_PLL_CFG_OUTDIV_GET(x) \
+ (((x) & AR934X_DDR_PLL_CFG_OUTDIV_MASK) >> \
+ AR934X_DDR_PLL_CFG_OUTDIV_LSB)
+
+#define AR934X_DDR_PLL_CFG_OUTDIV_SET(x) \
+ (((x) << AR934X_DDR_PLL_CFG_OUTDIV_LSB) & \
+ AR934X_DDR_PLL_CFG_OUTDIV_MASK)
+
+#define AR934X_CPU_PLL_CFG_REFDIV_MSB 16
+#define AR934X_CPU_PLL_CFG_REFDIV_LSB 12
+#define AR934X_CPU_PLL_CFG_REFDIV_MASK 0x0001f000
+
+#define AR934X_CPU_PLL_CFG_REFDIV_GET(x) \
+ (((x) & AR934X_CPU_PLL_CFG_REFDIV_MASK) >> \
+ AR934X_CPU_PLL_CFG_REFDIV_LSB)
+
+#define AR934X_CPU_PLL_CFG_REFDIV_SET(x) \
+ (((x) << AR934X_CPU_PLL_CFG_REFDIV_LSB) & \
+ AR934X_CPU_PLL_CFG_REFDIV_MASK)
+
+#define AR934X_CPU_PLL_CFG_REFDIV_RESET 2
+
+#define AR934X_CPU_PLL_CFG_NINT_MSB 11
+#define AR934X_CPU_PLL_CFG_NINT_LSB 6
+#define AR934X_CPU_PLL_CFG_NINT_MASK 0x00000fc0
+
+#define AR934X_CPU_PLL_CFG_NINT_GET(x) \
+ (((x) & AR934X_CPU_PLL_CFG_NINT_MASK) >> \
+ AR934X_CPU_PLL_CFG_NINT_LSB)
+
+#define AR934X_CPU_PLL_CFG_NINT_SET(x) \
+ (((x) << AR934X_CPU_PLL_CFG_NINT_LSB) & \
+ AR934X_CPU_PLL_CFG_NINT_MASK)
+
+#define AR934X_CPU_PLL_CFG_NINT_RESET 20
+
+#define AR934X_CPU_PLL_CFG_NFRAC_MSB 5
+#define AR934X_CPU_PLL_CFG_NFRAC_LSB 0
+#define AR934X_CPU_PLL_CFG_NFRAC_MASK 0x0000003f
+
+#define AR934X_CPU_PLL_CFG_NFRAC_GET(x) \
+ (((x) & AR934X_CPU_PLL_CFG_NFRAC_MASK) >> \
+ AR934X_CPU_PLL_CFG_NFRAC_LSB)
+
+#define AR934X_CPU_PLL_CFG_NFRAC_SET(x) \
+ (((x) << AR934X_CPU_PLL_CFG_NFRAC_LSB) & \
+ AR934X_CPU_PLL_CFG_NFRAC_MASK)
+
+#define AR934X_DDR_PLL_CFG_REFDIV_MSB 20
+#define AR934X_DDR_PLL_CFG_REFDIV_LSB 16
+#define AR934X_DDR_PLL_CFG_REFDIV_MASK 0x001f0000
+
+#define AR934X_DDR_PLL_CFG_REFDIV_GET(x) \
+ (((x) & AR934X_DDR_PLL_CFG_REFDIV_MASK) >> \
+ AR934X_DDR_PLL_CFG_REFDIV_LSB)
+
+#define AR934X_DDR_PLL_CFG_REFDIV_SET(x) \
+ (((x) << AR934X_DDR_PLL_CFG_REFDIV_LSB) & \
+ AR934X_DDR_PLL_CFG_REFDIV_MASK)
+
+#define AR934X_DDR_PLL_CFG_REFDIV_RESET 2
+
+#define AR934X_DDR_PLL_CFG_NINT_MSB 15
+#define AR934X_DDR_PLL_CFG_NINT_LSB 10
+#define AR934X_DDR_PLL_CFG_NINT_MASK 0x0000fc00
+
+#define AR934X_DDR_PLL_CFG_NINT_GET(x) \
+ (((x) & AR934X_DDR_PLL_CFG_NINT_MASK) >> \
+ AR934X_DDR_PLL_CFG_NINT_LSB)
+
+#define AR934X_DDR_PLL_CFG_NINT_SET(x) \
+ (((x) << AR934X_DDR_PLL_CFG_NINT_LSB) & \
+ AR934X_DDR_PLL_CFG_NINT_MASK)
+
+#define AR934X_DDR_PLL_CFG_NINT_RESET 20
+
+#define AR934X_DDR_PLL_CFG_NFRAC_MSB 9
+#define AR934X_DDR_PLL_CFG_NFRAC_LSB 0
+#define AR934X_DDR_PLL_CFG_NFRAC_MASK 0x000003ff
+
+#define AR934X_DDR_PLL_CFG_NFRAC_GET(x) \
+ (((x) & AR934X_DDR_PLL_CFG_NFRAC_MASK) >> \
+ AR934X_DDR_PLL_CFG_NFRAC_LSB)
+
+#define AR934X_DDR_PLL_CFG_NFRAC_SET(x) \
+ (((x) << AR934X_DDR_PLL_CFG_NFRAC_LSB) & \
+ AR934X_DDR_PLL_CFG_NFRAC_MASK)
+
+#define AR934X_DDR_PLL_CFG_NFRAC_RESET 512
+
+#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MSB 19
+#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB 15
+#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x000f8000
+
+#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(x) \
+ (((x) & AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK) >> \
+ AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB)
+
+#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SET(x) \
+ (((x) << AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB) & \
+ AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK)
+
+#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_RESET 0
+
+#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MSB 14
+#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB 10
+#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x00007c00
+
+#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(x) \
+ (((x) & AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK) >> \
+ AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB)
+
+#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SET(x) \
+ (((x) << AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB) & \
+ AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK)
+
+#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_RESET 0
+
+#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MSB 9
+#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB 5
+#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x000003e0
+
+#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(x) \
+ (((x) & AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK) >> \
+ AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB)
+
+#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SET(x) \
+ (((x) << AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB) & \
+ AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK)
+
+#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_RESET 0
+
+#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MSB 24
+#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB 24
+#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK 0x01000000
+
+#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(x) \
+ (((x) & AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK) >> \
+ AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB)
+
+#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SET(x) \
+ (((x) << AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB) & \
+ AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK)
+
+#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_RESET 1
+
extern void __iomem *ar71xx_pll_base;
static inline void ar71xx_pll_wr(unsigned reg, u32 val)
#define AR91XX_GPIO_COUNT 22
+#define AR933X_GPIO_COUNT 30
+
+#define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14)
+#define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13)
+
+#define AR934X_GPIO_COUNT 32
+#define AR934X_GPIO_FUNC_DDR_DQOE_EN BIT(17)
+
extern void __iomem *ar71xx_gpio_base;
static inline void ar71xx_gpio_wr(unsigned reg, u32 value)
void ar71xx_gpio_init(void) __init;
void ar71xx_gpio_function_enable(u32 mask);
void ar71xx_gpio_function_disable(u32 mask);
+void ar71xx_gpio_function_setup(u32 set, u32 clear);
/*
* DDR_CTRL block
#define AR91XX_DDR_REG_FLUSH_USB 0x84
#define AR91XX_DDR_REG_FLUSH_WMAC 0x88
+#define AR933X_DDR_REG_FLUSH_GE0 0x7c
+#define AR933X_DDR_REG_FLUSH_GE1 0x80
+#define AR933X_DDR_REG_FLUSH_USB 0x84
+#define AR933X_DDR_REG_FLUSH_WMAC 0x88
+
+#define AR934X_DDR_REG_FLUSH_GE0 0x9c
+#define AR934X_DDR_REG_FLUSH_GE1 0xa0
+#define AR934X_DDR_REG_FLUSH_USB 0xa4
+#define AR934X_DDR_REG_FLUSH_PCIE 0xa8
+
+
#define PCI_WIN0_OFFS 0x10000000
#define PCI_WIN1_OFFS 0x11000000
#define PCI_WIN2_OFFS 0x12000000
#define AR724X_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + 0x4000000)
#define AR724X_PCI_CFG_SIZE 0x1000
+#define AR724X_PCI_REG_APP 0x00
+#define AR724X_PCI_REG_RESET 0x18
#define AR724X_PCI_REG_INT_STATUS 0x4c
#define AR724X_PCI_REG_INT_MASK 0x50
-#define AR724X_PCI_INT_DEV0 BIT(14)
-
-static inline void ar724x_pci_wr(unsigned reg, u32 val)
-{
- void __iomem *base;
-
- base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
- __raw_writel(val, base + reg);
- iounmap(base);
-}
-
-static inline u32 ar724x_pci_rr(unsigned reg)
-{
- void __iomem *base;
- u32 ret;
+#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0)
+#define AR724X_PCI_RESET_LINK_UP BIT(0)
- base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
- ret = __raw_readl(base + reg);
- iounmap(base);
- return ret;
-}
+#define AR724X_PCI_INT_DEV0 BIT(14)
/*
* RESET block
#define AR724X_RESET_REG_RESET_MODULE 0x1c
+#define AR933X_RESET_REG_RESET_MODULE 0x1c
+#define AR933X_RESET_REG_BOOTSTRAP 0xac
+#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
+#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
+
+#define AR934X_RESET_REG_RESET_MODULE 0x1c
+#define AR934X_RESET_REG_BOOTSTRAP 0xb0
+/* 0 - 25MHz 1 - 40 MHz */
+#define AR934X_REF_CLK_40 (1 << 4)
+
#define WDOG_CTRL_LAST_RESET BIT(31)
#define WDOG_CTRL_ACTION_MASK 3
#define WDOG_CTRL_ACTION_NONE 0 /* no action */
#define WDOG_CTRL_ACTION_NMI 2 /* NMI */
#define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */
+#define MISC_INT_ENET_LINK BIT(12)
+#define MISC_INT_DDR_PERF BIT(11)
+#define MISC_INT_TIMER4 BIT(10)
+#define MISC_INT_TIMER3 BIT(9)
+#define MISC_INT_TIMER2 BIT(8)
#define MISC_INT_DMA BIT(7)
#define MISC_INT_OHCI BIT(6)
#define MISC_INT_PERFC BIT(5)
#define RESET_MODULE_PCI_BUS BIT(1)
#define RESET_MODULE_PCI_CORE BIT(0)
-#define REV_ID_MAJOR_MASK 0xf0
-#define REV_ID_MAJOR_AR71XX 0xa0
-#define REV_ID_MAJOR_AR913X 0xb0
-#define REV_ID_MAJOR_AR724X 0xc0
+#define AR724X_RESET_GE1_MDIO BIT(23)
+#define AR724X_RESET_GE0_MDIO BIT(22)
+#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
+#define AR724X_RESET_PCIE_PHY BIT(7)
+#define AR724X_RESET_PCIE BIT(6)
+#define AR724X_RESET_USB_HOST BIT(5)
+#define AR724X_RESET_USB_PHY BIT(4)
+#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
+
+#define AR933X_RESET_WMAC BIT(11)
+#define AR933X_RESET_GE1_MDIO BIT(23)
+#define AR933X_RESET_GE0_MDIO BIT(22)
+#define AR933X_RESET_GE1_MAC BIT(13)
+#define AR933X_RESET_GE0_MAC BIT(9)
+
+#define REV_ID_MAJOR_MASK 0xfff0
+#define REV_ID_MAJOR_AR71XX 0x00a0
+#define REV_ID_MAJOR_AR913X 0x00b0
+#define REV_ID_MAJOR_AR7240 0x00c0
+#define REV_ID_MAJOR_AR7241 0x0100
+#define REV_ID_MAJOR_AR7242 0x1100
+#define REV_ID_MAJOR_AR9330 0x0110
+#define REV_ID_MAJOR_AR9331 0x1110
+#define REV_ID_MAJOR_AR9341 0x0120
+#define REV_ID_MAJOR_AR9342 0x1120
+#define REV_ID_MAJOR_AR9344 0x2120
#define AR71XX_REV_ID_MINOR_MASK 0x3
#define AR71XX_REV_ID_MINOR_AR7130 0x0
#define AR724X_REV_ID_REVISION_MASK 0x3
+#define AR933X_REV_ID_REVISION_MASK 0xf
+
+#define AR934X_REV_ID_REVISION_MASK 0xf
+
extern void __iomem *ar71xx_reset_base;
static inline void ar71xx_reset_wr(unsigned reg, u32 val)
void ar71xx_device_stop(u32 mask);
void ar71xx_device_start(u32 mask);
+int ar71xx_device_stopped(u32 mask);
/*
* SPI block
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