ar71xx: fix MDIO access on ar7242 (based on a patch by Jess Zhu)

[openwrt.git] / target / linux / ar71xx / files / arch / mips / include / asm / mach-ar71xx / ar71xx.h

diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
index ab00d19..48c4a73 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
@@ -70,6 +70,9 @@
 #define AR91XX_WMAC_BASE       (AR71XX_APB_BASE + 0x000C0000)
 #define AR91XX_WMAC_SIZE       0x30000
 
+#define AR934X_WMAC_BASE       (AR71XX_APB_BASE + 0x00100000)
+#define AR934X_WMAC_SIZE       0x20000
+
 #define AR71XX_MEM_SIZE_MIN    0x0200000
 #define AR71XX_MEM_SIZE_MAX    0x10000000
 
@@ -112,7 +115,7 @@
 extern u32 ar71xx_ahb_freq;
 extern u32 ar71xx_cpu_freq;
 extern u32 ar71xx_ddr_freq;
-extern u32 ar934x_ref_freq;
+extern u32 ar71xx_ref_freq;
 
 enum ar71xx_soc_type {
        AR71XX_SOC_UNKNOWN,
@@ -163,6 +166,8 @@ extern enum ar71xx_soc_type ar71xx_soc;
 #define AR724X_DDR_DIV_SHIFT           22
 #define AR724X_DDR_DIV_MASK            0x3
 
+#define AR7242_PLL_REG_ETH0_INT_CLOCK  0x2c
+
 #define AR91XX_PLL_REG_CPU_CONFIG      0x00
 #define AR91XX_PLL_REG_ETH_CONFIG      0x04
 #define AR91XX_PLL_REG_ETH0_INT_CLOCK  0x14
@@ -427,6 +432,12 @@ static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
 
 #define AR91XX_GPIO_COUNT      22
 
+#define AR934X_GPIO_FUNC_SPI_CS_1_EN   BIT(14)
+#define AR934X_GPIO_FUNC_SPI_CS_0_EN   BIT(13)
+
+#define AR934X_GPIO_COUNT              32
+#define AR934X_GPIO_FUNC_DDR_DQOE_EN   BIT(17)
+
 extern void __iomem *ar71xx_gpio_base;
 
 static inline void ar71xx_gpio_wr(unsigned reg, u32 value)