-+ ERRCS_wto_b = 0, // In INTEG_t -> errcs
-+ ERRCS_wto_m = 0x00000001,
-+ ERRCS_wne_b = 1, // In INTEG_t -> errcs
-+ ERRCS_wne_m = 0x00000002,
-+ ERRCS_ucw_b = 2, // In INTEG_t -> errcs
-+ ERRCS_ucw_m = 0x00000004,
-+ ERRCS_ucr_b = 3, // In INTEG_t -> errcs
-+ ERRCS_ucr_m = 0x00000008,
-+ ERRCS_upw_b = 4, // In INTEG_t -> errcs
-+ ERRCS_upw_m = 0x00000010,
-+ ERRCS_upr_b = 5, // In INTEG_t -> errcs
-+ ERRCS_upr_m = 0x00000020,
-+ ERRCS_udw_b = 6, // In INTEG_t -> errcs
-+ ERRCS_udw_m = 0x00000040,
-+ ERRCS_udr_b = 7, // In INTEG_t -> errcs
-+ ERRCS_udr_m = 0x00000080,
-+ ERRCS_sae_b = 8, // In INTEG_t -> errcs
-+ ERRCS_sae_m = 0x00000100,
-+ ERRCS_wre_b = 9, // In INTEG_t -> errcs
-+ ERRCS_wre_m = 0x00000200,
-+
-+ WTC_en_b = 0, // In INTEG_t -> wtc
-+ WTC_en_m = 0x00000001,
-+ WTC_to_b = 1, // In INTEG_t -> wtc
-+ WTC_to_m = 0x00000002,
-+} ;
-+
-+#endif // __IDT_INTEG_H__
-diff -urN linux.old/include/asm-mips/rc32434/int.h linux.dev/include/asm-mips/rc32434/int.h
---- linux.old/include/asm-mips/rc32434/int.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/int.h 2006-12-14 04:09:50.000000000 +0100
-@@ -0,0 +1,167 @@
-+#ifndef __IDT_INT_H__
-+#define __IDT_INT_H__
-+
-+/*******************************************************************************
-+ *
-+ * Copyright 2002 Integrated Device Technology, Inc.
-+ * All rights reserved.
-+ *
-+ * Interrupt Controller register definition.
-+ *
-+ * File : $Id: int.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
-+ *
-+ * Author : ryan.holmqvist@idt.com
-+ * Date : 20011005
-+ * Update :
-+ * $Log: int.h,v $
-+ * Revision 1.3 2002/06/06 18:34:04 astichte
-+ * Added XXX_PhysicalAddress and XXX_VirtualAddress
-+ *
-+ * Revision 1.2 2002/06/05 18:47:33 astichte
-+ * Removed IDTField
-+ *
-+ * Revision 1.1 2002/05/29 17:33:22 sysarch
-+ * jba File moved from vcode/include/idt/acacia
-+ *
-+ *
-+ ******************************************************************************/
-+
-+#include <asm/rc32434/types.h>
-+
-+enum
-+{
-+ INT0_PhysicalAddress = 0x18038000,
-+ INT_PhysicalAddress = INT0_PhysicalAddress, // Default
-+
-+ INT0_VirtualAddress = 0xb8038000,
-+ INT_VirtualAddress = INT0_VirtualAddress, // Default
-+} ;
-+
-+struct INT_s
-+{
-+ U32 ipend ; //Pending interrupts. use INT?_
-+ U32 itest ; //Test bits. use INT?_
-+ U32 imask ; //Interrupt disabled when set. use INT?_
-+} ;
-+
-+enum
-+{
-+ IPEND2 = 0, // HW 2 interrupt to core. use INT2_
-+ IPEND3 = 1, // HW 3 interrupt to core. use INT3_
-+ IPEND4 = 2, // HW 4 interrupt to core. use INT4_
-+ IPEND5 = 3, // HW 5 interrupt to core. use INT5_
-+ IPEND6 = 4, // HW 6 interrupt to core. use INT6_
-+
-+ IPEND_count, // must be last (used in loops)
-+ IPEND_min = IPEND2 // min IPEND (used in loops)
-+};
-+
-+typedef struct INTC_s
-+{
-+ struct INT_s i [IPEND_count] ;// use i[IPEND?] = INT?_
-+ U32 nmips ; // use NMIPS_
-+} volatile *INT_t ;
-+
-+enum
-+{
-+ INT2_timer0_b = 0,
-+ INT2_timer0_m = 0x00000001,
-+ INT2_timer1_b = 1,
-+ INT2_timer1_m = 0x00000002,
-+ INT2_timer2_b = 2,
-+ INT2_timer2_m = 0x00000004,
-+ INT2_refresh_b = 3,
-+ INT2_refresh_m = 0x00000008,
-+ INT2_watchdogTimeout_b = 4,
-+ INT2_watchdogTimeout_m = 0x00000010,
-+ INT2_undecodedCpuWrite_b = 5,
-+ INT2_undecodedCpuWrite_m = 0x00000020,
-+ INT2_undecodedCpuRead_b = 6,
-+ INT2_undecodedCpuRead_m = 0x00000040,
-+ INT2_undecodedPciWrite_b = 7,
-+ INT2_undecodedPciWrite_m = 0x00000080,
-+ INT2_undecodedPciRead_b = 8,
-+ INT2_undecodedPciRead_m = 0x00000100,
-+ INT2_undecodedDmaWrite_b = 9,
-+ INT2_undecodedDmaWrite_m = 0x00000200,
-+ INT2_undecodedDmaRead_b = 10,
-+ INT2_undecodedDmaRead_m = 0x00000400,
-+ INT2_ipBusSlaveAckError_b = 11,
-+ INT2_ipBusSlaveAckError_m = 0x00000800,
-+
-+ INT3_dmaChannel0_b = 0,
-+ INT3_dmaChannel0_m = 0x00000001,
-+ INT3_dmaChannel1_b = 1,
-+ INT3_dmaChannel1_m = 0x00000002,
-+ INT3_dmaChannel2_b = 2,
-+ INT3_dmaChannel2_m = 0x00000004,
-+ INT3_dmaChannel3_b = 3,
-+ INT3_dmaChannel3_m = 0x00000008,
-+ INT3_dmaChannel4_b = 4,
-+ INT3_dmaChannel4_m = 0x00000010,
-+ INT3_dmaChannel5_b = 5,
-+ INT3_dmaChannel5_m = 0x00000020,
-+
-+ INT5_uartGeneral0_b = 0,
-+ INT5_uartGeneral0_m = 0x00000001,
-+ INT5_uartTxrdy0_b = 1,
-+ INT5_uartTxrdy0_m = 0x00000002,
-+ INT5_uartRxrdy0_b = 2,
-+ INT5_uartRxrdy0_m = 0x00000004,
-+ INT5_pci_b = 3,
-+ INT5_pci_m = 0x00000008,
-+ INT5_pciDecoupled_b = 4,
-+ INT5_pciDecoupled_m = 0x00000010,
-+ INT5_spi_b = 5,
-+ INT5_spi_m = 0x00000020,
-+ INT5_deviceDecoupled_b = 6,
-+ INT5_deviceDecoupled_m = 0x00000040,
-+ INT5_i2cMaster_b = 7,
-+ INT5_i2cMaster_m = 0x00000080,
-+ INT5_i2cSlave_b = 8,
-+ INT5_i2cSlave_m = 0x00000100,
-+ INT5_ethOvr_b = 9,
-+ INT5_ethOvr_m = 0x00000200,
-+ INT5_ethUnd_b = 10,
-+ INT5_ethUnd_m = 0x00000400,
-+ INT5_ethPfd_b = 11,
-+ INT5_ethPfd_m = 0x00000800,
-+ INT5_nvram_b = 12,
-+ INT5_nvram_m = 0x00001000,
-+
-+ INT6_gpio0_b = 0,
-+ INT6_gpio0_m = 0x00000001,
-+ INT6_gpio1_b = 1,
-+ INT6_gpio1_m = 0x00000002,
-+ INT6_gpio2_b = 2,
-+ INT6_gpio2_m = 0x00000004,
-+ INT6_gpio3_b = 3,
-+ INT6_gpio3_m = 0x00000008,
-+ INT6_gpio4_b = 4,
-+ INT6_gpio4_m = 0x00000010,
-+ INT6_gpio5_b = 5,
-+ INT6_gpio5_m = 0x00000020,
-+ INT6_gpio6_b = 6,
-+ INT6_gpio6_m = 0x00000040,
-+ INT6_gpio7_b = 7,
-+ INT6_gpio7_m = 0x00000080,
-+ INT6_gpio8_b = 8,
-+ INT6_gpio8_m = 0x00000100,
-+ INT6_gpio9_b = 9,
-+ INT6_gpio9_m = 0x00000200,
-+ INT6_gpio10_b = 10,
-+ INT6_gpio10_m = 0x00000400,
-+ INT6_gpio11_b = 11,
-+ INT6_gpio11_m = 0x00000800,
-+ INT6_gpio12_b = 12,
-+ INT6_gpio12_m = 0x00001000,
-+ INT6_gpio13_b = 13,
-+ INT6_gpio13_m = 0x00002000,
-+
-+ NMIPS_gpio_b = 0,
-+ NMIPS_gpio_m = 0x00000001,
-+} ;
-+
-+#endif // __IDT_INT_H__
-+
-+
-diff -urN linux.old/include/asm-mips/rc32434/iparb.h linux.dev/include/asm-mips/rc32434/iparb.h
---- linux.old/include/asm-mips/rc32434/iparb.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/iparb.h 2006-12-14 04:09:50.000000000 +0100
-@@ -0,0 +1,95 @@
-+#ifndef __IDT_IPARB_H__
-+#define __IDT_IPARB_H__
-+
-+/*******************************************************************************
-+ *
-+ * Copyright 2002 Integrated Device Technology, Inc.
-+ * All rights reserved.
-+ *
-+ * IP Arbiter register definitions.
-+ *
-+ * File : $Id: iparb.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
-+ *
-+ * Author : Allen.Stichter@idt.com
-+ * Date : 20020120
-+ * Update :
-+ * $Log: iparb.h,v $
-+ * Revision 1.3 2002/06/06 18:34:04 astichte
-+ * Added XXX_PhysicalAddress and XXX_VirtualAddress
-+ *
-+ * Revision 1.2 2002/06/05 19:01:42 astichte
-+ * Removed IDTField
-+ *
-+ * Revision 1.1 2002/05/29 17:33:23 sysarch
-+ * jba File moved from vcode/include/idt/acacia
-+ *
-+ ******************************************************************************/
-+
-+#include <asm/rc32434/types.h>
-+
-+enum
-+{
-+ IPARB0_PhysicalAddress = 0x18048000,
-+ IPARB_PhysicalAddress = IPARB0_PhysicalAddress, // Default
-+
-+ IPARB0_VirtualAddress = 0xb8048000,
-+ IPARB_VirtualAddress = IPARB0_VirtualAddress, // Default
-+} ;
-+
-+enum
-+{
-+ IPABMXC_ethernetReceive = 0,
-+ IPABMXC_ethernetTransmit = 1,
-+ IPABMXC_memoryToHoldFifo = 2,
-+ IPABMXC_holdFifoToMemory = 3,
-+ IPABMXC_pciToMemory = 4,
-+ IPABMXC_memoryToPci = 5,
-+ IPABMXC_pciTarget = 6,
-+ IPABMXC_pciTargetStart = 7,
-+ IPABMXC_cpuToIpBus = 8,
-+
-+ IPABMXC_Count, // Must be last in list !
-+ IPABMXC_Min = IPABMXC_ethernetReceive,
-+
-+ IPAPXC_PriorityCount = 4, // 3-highest, 0-lowest.
-+} ;
-+
-+typedef struct
-+{
-+ U32 ipapc [IPAPXC_PriorityCount] ; // ipapc[IPAPXC_] = IPAPC_
-+ U32 ipabmc [IPABMXC_Count] ; // ipabmc[IPABMXC_] = IPABMC_
-+ U32 ipac ; // use IPAC_
-+ U32 ipaitcc; // use IPAITCC_
-+ U32 ipaspare ;
-+} volatile * IPARB_t ;
-+
-+enum
-+{
-+ IPAC_dwm_b = 2,
-+ IPAC_dwm_m = 0x00000004,
-+ IPAC_drm_b = 3,
-+ IPAC_drm_m = 0x00000008,
-+ IPAC_msk_b = 4,
-+ IPAC_msk_m = 0x00000010,
-+
-+ IPAPC_ptc_b = 0,
-+ IPAPC_ptc_m = 0x00003fff,
-+ IPAPC_mf_b = 14,
-+ IPAPC_mf_m = 0x00004000,
-+ IPAPC_cptc_b = 16,
-+ IPAPC_cptc_m = 0x3fff0000,
-+
-+ IPAITCC_itcc = 0,
-+ IPAITCC_itcc, = 0x000001ff,
-+
-+ IPABMC_mtc_b = 0,
-+ IPABMC_mtc_m = 0x00000fff,
-+ IPABMC_p_b = 12,
-+ IPABMC_p_m = 0x00003000,
-+ IPABMC_msk_b = 14,
-+ IPABMC_msk_m = 0x00004000,
-+ IPABMC_cmtc_b = 16,
-+ IPABMC_cmtc_m = 0x0fff0000,
-+};
-+
-+#endif // __IDT_IPARB_H__
-diff -urN linux.old/include/asm-mips/rc32434/irm.h linux.dev/include/asm-mips/rc32434/irm.h
---- linux.old/include/asm-mips/rc32434/irm.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/irm.h 2006-12-14 04:09:50.000000000 +0100
-@@ -0,0 +1,55 @@
-+#ifndef __IDT_IRM_H__
-+#define __IDT_IRM_H__
-+
-+/*******************************************************************************
-+ *
-+ * Copyright 2002 Integrated Device Technology, Inc.
-+ * All rights reserved.
-+ *
-+ * Internal Register Map
-+ *
-+ * File : $Id: irm.h,v 1.2 2002/06/05 14:51:06 astichte Exp $
-+ *
-+ * Author : Allen.Stichter@idt.com
-+ * Date : 20020605
-+ * Update :
-+ * $Log: irm.h,v $
-+ * Revision 1.2 2002/06/05 14:51:06 astichte
-+ * *** empty log message ***
-+ *
-+ * Revision 1.1 2002/05/29 17:33:23 sysarch
-+ * jba File moved from vcode/include/idt/acacia
-+ *
-+ ******************************************************************************/
-+
-+/*
-+ * NOTE --
-+ * This file is here for backwards compatibility.
-+ * DO NOT USE !!!!
-+ */
-+
-+typedef enum
-+{
-+ IRM_Physical = 0x18000000, // Internal Reg. map physical.
-+ RST_Offset = 0x00000000, // Includes sysid and RST.
-+ DEV_Offset = 0x00010000, // Device Controller 0.
-+ DDR_Offset = 0x00018000, // Double-Data-Rate mem. controller.
-+ PMARB_Offset = 0x00020000, // PM bus arbiter.
-+ TIM_Offset = 0x00028000, // Counter / timer.
-+ INTEG_Offset = 0x00030000, // System Integrity.
-+ INT_Offset = 0x00038000, // Interrupt controller.
-+ DMA_Offset = 0x00040000, // DMA.
-+ IPARB_Offset = 0x00044000, // IP bus arbiter.
-+ GPIO_Offset = 0x00050000, // GPIO.
-+ UART_Offset = 0x00058000, // UART
-+ ETH_Offset = 0x00060000, // Ethernet 1.
-+ I2C_Offset = 0x00068000, // I2C interface.
-+ SPI_Offset = 0x00070000, // Serial Peripheral Interface.
-+ NVRAM_Offset = 0x00078000, // NVRAM interface
-+ AUTH_Offset = 0x0007c000, // Authorization unit
-+ PCI_Offset = 0x00080000,
-+ CROM_Offset = 0x000b8000, // Configuration ROM.
-+ IRM_Size = 0x00200000, // Internal Reg. map size.
-+} IRM_Offset_t ;
-+
-+#endif // __IDT_IRM_H__
-diff -urN linux.old/include/asm-mips/rc32434/irq.h linux.dev/include/asm-mips/rc32434/irq.h
---- linux.old/include/asm-mips/rc32434/irq.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/irq.h 2006-12-14 04:09:50.000000000 +0100
-@@ -0,0 +1,8 @@
-+#ifndef __ASM_MACH_MIPS_IRQ_H
-+#define __ASM_MACH_MIPS_IRQ_H
-+
-+#include <linux/autoconf.h>
-+
-+#define NR_IRQS 256
-+
-+#endif /* __ASM_MACH_MIPS_IRQ_H */
-diff -urN linux.old/include/asm-mips/rc32434/nvram.h linux.dev/include/asm-mips/rc32434/nvram.h
---- linux.old/include/asm-mips/rc32434/nvram.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/nvram.h 2006-12-14 04:09:50.000000000 +0100
-@@ -0,0 +1,97 @@
-+#ifndef __IDT_NVRAM_H
-+#define __IDT_NVRAM_H
-+
-+/*******************************************************************************
-+ *
-+ * Copyright 2002 Integrated Device Technology, Inc.
-+ * All rights reserved.
-+ *
-+ * IP Arbiter register definitions.
-+ *
-+ * File : $Id: nvram.h,v 1.3 2003/07/24 18:34:04 astichte Exp $
-+ *
-+ * Author : kiran.rao@idt.com
-+ * Date : 20030724
-+ * Update :
-+ * $Log: nvram.h,v $
-+ *
-+ *
-+ ******************************************************************************/
-+#include <asm/rc32434/tpes.h>
-+
-+
-+enum
-+{
-+ NVRAM0_PhysicalAddress = 0xba000000,
-+ NVRAM_PhysicalAddress = NVRAM0_PhysicalAddress, // Default
-+
-+ NVRAM0_VirtualAddress = 0xba000000,
-+ NVRAM_VirtualAddress = NVRAM0_VirtualAddress, // Default
-+} ;
-+
-+enum
-+{
-+ NVRCMD_cmd_b = 0,
-+ NVRCMD_cmd_m = 0x0000007f,
-+
-+ NVRS_r_b = 0,
-+ NVRS_r_m = 0x00000001,
-+ NVRS_e_b = 1,
-+ NVRS_e_m = 0x00000002,
-+ NVRS_k_b = 2,
-+ NVRS_k_m = 0x00000004,
-+
-+ NVRSM_r_b = 0,
-+ NVRSM_r_m = 0x00000001,
-+ NVRSM_e_b = 1,
-+ NVRSM_e_m = 0x00000002,
-+ NVRSM_k_b = 2,
-+ NVRSM_k_m = 0x00000004,
-+
-+ NVRCFG0_pwidth_b = 0,
-+ NVRCFG0_pwidth_m = 0x00000003,
-+ NVRCFG0_nmax_b = 2,
-+ NVRCFG0_nmax_m = 0x0000000C,
-+ NVRCFG0_vppl_b = 4,
-+ NVRCFG0_vppl_m = 0x000000f0,
-+ NVRCFG0_vppm_b = 8,
-+ NVRCFG0_vppm_m = 0x00000300,
-+ NVRCFG0_dvpp_b = 10,
-+ NVRCFG0_dvpp_m = 0x00000c00,
-+ NVRCFG0_x_b = 12,
-+ NVRCFG0_x_m = 0x00007000,
-+
-+ NVRCFG1_t1tecc_b = 0,
-+ NVRCFG1_t1tecc_m = 0x00000003,
-+ NVRCFG1_t1mrcl_b = 2,
-+ NVRCFG1_t1mrcl_m = 0x0000000c,
-+ NVRCFG1_t1bias_b = 4,
-+ NVRCFG1_t1bias_m = 0x00000030,
-+ NVRCFG1_t2tecc_b = 6,
-+ NVRCFG1_t2tecc_m = 0x000000c0,
-+ NVRCFG1_t2mrcl_b = 8,
-+ NVRCFG1_t2mrcl_m = 0x00000300,
-+ NVRCFG1_t2bias_b = 10,
-+ NVRCFG1_t2bias_m = 0x00000c00,
-+ NVRCFG1_t3tecc_b = 12,
-+ NVRCFG1_t3tecc_m = 0x00003000,
-+ NVRCFG1_t3mrcl_b = 14,
-+ NVRCFG1_t3mrcl_m = 0x0000c000,
-+ NVRCFG1_t3bias_b = 16,
-+ NVRCFG1_t3bias_m = 0x00030000,
-+ NVRCFG1_t4tecc_b = 18,
-+ NVRCFG1_t4tecc_m = 0x000c0000,
-+ NVRCFG1_t4mrcl_b = 20,
-+ NVRCFG1_t4mrcl_m = 0x00300000,
-+ NVRCFG1_t4bias_b = 22,
-+ NVRCFG1_t4bias_m = 0x00c00000,
-+ NVRCFG1_t5tecc_b = 24,
-+ NVRCFG1_t5tecc_m = 0x03000000,
-+ NVRCFG1_t5mrcl_b = 26,
-+ NVRCFG1_t5mrcl_m = 0x0c000000,
-+ NVRCFG1_t5bias_b = 28,
-+ NVRCFG1_t5bias_m = 0x30000000,
-+}
-+
-+#endif // __IDT_NVRAM_H__
-+
-diff -urN linux.old/include/asm-mips/rc32434/pci.h linux.dev/include/asm-mips/rc32434/pci.h
---- linux.old/include/asm-mips/rc32434/pci.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/include/asm-mips/rc32434/pci.h 2006-12-14 04:09:50.000000000 +0100
-@@ -0,0 +1,695 @@
-+/**************************************************************************
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ * PCI register definitio
-+ *
-+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ *
-+ **************************************************************************
-+ * May 2004 rkt, neb.
-+ *
-+ * Initial Release
-+ *
-+ *
-+ *
-+ **************************************************************************
-+ */
-+
-+#ifndef __IDT_PCI_H__
-+#define __IDT_PCI_H__
-+
-+enum
-+{
-+ PCI0_PhysicalAddress = 0x18080000,
-+ PCI_PhysicalAddress = PCI0_PhysicalAddress,
-+
-+ PCI0_VirtualAddress = 0xB8080000,
-+ PCI_VirtualAddress = PCI0_VirtualAddress,
-+} ;
-+
-+enum
-+{
-+ PCI_LbaCount = 4, // Local base addresses.
projects / openwrt.git / blobdiff