ar71xx: set a reserved bit that resets to 1 when writing the address table control...

[openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_ar7240.c

diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_ar7240.c b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_ar7240.c
index ae211be..491127d 100644 (file)
--- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_ar7240.c
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_ar7240.c
@@ -66,6 +66,7 @@
 #define AR7240_AT_CTRL_AGE_TIME                BITS(0, 15)
 #define AR7240_AT_CTRL_AGE_EN          BIT(17)
 #define AR7240_AT_CTRL_LEARN_CHANGE    BIT(18)
+#define AR7240_AT_CTRL_RESERVED                BIT(19)
 #define AR7240_AT_CTRL_ARP_EN          BIT(20)
 
 #define AR7240_REG_TAG_PRIORITY                0x70
@@ -203,6 +204,29 @@
 #define   AR934X_OPER_MODE0_MAC_GMII_EN        BIT(6)
 #define   AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
 
+#define AR934X_REG_OPER_MODE1          0x08
+#define   AR934X_REG_OPER_MODE1_PHY4_MII_EN    BIT(28)
+
+#define AR934X_REG_PORT_BASE(_port)    (0x100 + (_port) * 0x100)
+
+#define AR934X_REG_PORT_VLAN1(_port)   (AR934X_REG_PORT_BASE((_port)) + 0x08)
+#define   AR934X_PORT_VLAN1_DEFAULT_SVID_S             0
+#define   AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN       BIT(12)
+#define   AR934X_PORT_VLAN1_PORT_TLS_MODE              BIT(13)
+#define   AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN          BIT(14)
+#define   AR934X_PORT_VLAN1_PORT_CLONE_EN              BIT(15)
+#define   AR934X_PORT_VLAN1_DEFAULT_CVID_S             16
+#define   AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN         BIT(28)
+#define   AR934X_PORT_VLAN1_ING_PORT_PRI_S             29
+
+#define AR934X_REG_PORT_VLAN2(_port)   (AR934X_REG_PORT_BASE((_port)) + 0x0c)
+#define   AR934X_PORT_VLAN2_PORT_VID_MEM_S             16
+#define   AR934X_PORT_VLAN2_8021Q_MODE_S               30
+#define   AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY       0
+#define   AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK   1
+#define   AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY       2
+#define   AR934X_PORT_VLAN2_8021Q_MODE_SECURE          3
+
 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
 
 struct ar7240sw {
@@ -447,6 +471,7 @@ static void ar7240sw_setup(struct ar7240sw *as)
 
        /* Enable ARP frame acknowledge, aging, MAC replacing */
        ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
+               AR7240_AT_CTRL_RESERVED |
                0x2b /* 5 min age time */ |
                AR7240_AT_CTRL_AGE_EN |
                AR7240_AT_CTRL_ARP_EN |
@@ -492,7 +517,7 @@ static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
 {
        struct mii_bus *mii = as->mii_bus;
        u32 ctrl;
-       u32 vlan;
+       u32 vid, mode;
 
        ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
                AR7240_PORT_CTRL_SINGLE_VLAN;
@@ -512,13 +537,11 @@ static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
 
        /* Set the default VID for this port */
        if (as->vlan) {
-               vlan = as->vlan_id[as->pvid[port]];
-               vlan |= AR7240_PORT_VLAN_MODE_SECURE <<
-                       AR7240_PORT_VLAN_MODE_S;
+               vid = as->vlan_id[as->pvid[port]];
+               mode = AR7240_PORT_VLAN_MODE_SECURE;
        } else {
-               vlan = port;
-               vlan |= AR7240_PORT_VLAN_MODE_PORT_ONLY <<
-                       AR7240_PORT_VLAN_MODE_S;
+               vid = port;
+               mode = AR7240_PORT_VLAN_MODE_PORT_ONLY;
        }
 
        if (as->vlan && (as->vlan_tagged & BIT(port))) {
@@ -541,11 +564,23 @@ static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
         * port that they came from */
        portmask &= ar7240sw_port_mask_but(as, port);
 
-       /* set default VID and and destination ports for this VLAN */
-       vlan |= (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
-
        ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
-       ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
+       if (sw_is_ar934x(as)) {
+               u32 vlan1, vlan2;
+
+               vlan1 = (vid << AR934X_PORT_VLAN1_DEFAULT_CVID_S);
+               vlan2 = (portmask << AR934X_PORT_VLAN2_PORT_VID_MEM_S) |
+                       (mode << AR934X_PORT_VLAN2_8021Q_MODE_S);
+               ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN1(port), vlan1);
+               ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN2(port), vlan2);
+       } else {
+               u32 vlan;
+
+               vlan = vid | (mode << AR7240_PORT_VLAN_MODE_S) |
+                      (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
+
+               ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
+       }
 }
 
 static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
@@ -898,11 +933,8 @@ static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
        if (sw_is_ar7240(as)) {
                swdev->name = "AR7240/AR9330 built-in switch";
        } else if (sw_is_ar934x(as)) {
-               struct ag71xx_platform_data *pdata;
-
                swdev->name = "AR934X built-in switch";
 
-               pdata = ag71xx_get_pdata(ag);
                if (pdata->phy_if_mode == PHY_INTERFACE_MODE_GMII) {
                        ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
                                         AR934X_OPER_MODE0_MAC_GMII_EN);
@@ -914,6 +946,10 @@ static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
                               ag->dev->name);
                        goto err_free;
                }
+
+               if (as->swdata->phy4_mii_en)
+                       ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE1,
+                                        AR934X_REG_OPER_MODE1_PHY4_MII_EN);
        } else {
                pr_err("%s: unsupported chip, ctrl=%08x\n",
                        ag->dev->name, ctrl);