#define AR91XX_WMAC_SIZE 0x30000
#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
-#define AR934X_WMAC_SIZE 0x1ffff
+#define AR934X_WMAC_SIZE 0x20000
#define AR71XX_MEM_SIZE_MIN 0x0200000
#define AR71XX_MEM_SIZE_MAX 0x10000000
extern u32 ar71xx_ahb_freq;
extern u32 ar71xx_cpu_freq;
extern u32 ar71xx_ddr_freq;
-extern u32 ar934x_ref_freq;
+extern u32 ar71xx_ref_freq;
enum ar71xx_soc_type {
AR71XX_SOC_UNKNOWN,
#define AR724X_DDR_DIV_SHIFT 22
#define AR724X_DDR_DIV_MASK 0x3
+#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
+
#define AR91XX_PLL_REG_CPU_CONFIG 0x00
#define AR91XX_PLL_REG_ETH_CONFIG 0x04
#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14