Disable NAPI by default (#1671)

[openwrt.git] / target / linux / ar7-2.6 / files / include / asm-mips / ar7 / ar7.h

diff --git a/target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h b/target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h
index a5fa474..49e66ff 100644 (file)
--- a/target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h
+++ b/target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h
@@ -21,38 +21,36 @@
 #ifndef __AR7_H__
 #define __AR7_H__
 
-#include <asm/addrspace.h>
 #include <linux/delay.h>
+#include <asm/addrspace.h>
+#include <asm/io.h>
 
 #define AR7_REGS_BASE 0x08610000
 
 #define AR7_REGS_MAC0   (AR7_REGS_BASE + 0x0000)
-#define AR7_REGS_EMIF   (AR7_REGS_BASE + 0x0800)
 #define AR7_REGS_GPIO   (AR7_REGS_BASE + 0x0900)
-#define AR7_REGS_POWER  (AR7_REGS_BASE + 0x0a00)
-#define AR7_REGS_WDT    (AR7_REGS_BASE + 0x0b00)
-#define AR7_REGS_TIMER0 (AR7_REGS_BASE + 0x0c00)
-#define AR7_REGS_TIMER1 (AR7_REGS_BASE + 0x0d00)
+#define AR7_REGS_POWER  (AR7_REGS_BASE + 0x0a00) // 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock)
 #define AR7_REGS_UART0  (AR7_REGS_BASE + 0x0e00)
-#define AR7_REGS_UART1  (AR7_REGS_BASE + 0x0f00)
-#define AR7_REGS_I2C    (AR7_REGS_BASE + 0x1000)
-#define AR7_REGS_USB    (AR7_REGS_BASE + 0x1200)
-#define AR7_REGS_DMA    (AR7_REGS_BASE + 0x1400)
 #define AR7_REGS_RESET  (AR7_REGS_BASE + 0x1600)
-#define AR7_REGS_BIST   (AR7_REGS_BASE + 0x1700)
 #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
 #define AR7_REGS_DCL    (AR7_REGS_BASE + 0x1A00)
 #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1C00)
 #define AR7_REGS_MDIO   (AR7_REGS_BASE + 0x1E00)
-#define AR7_REGS_FSER   (AR7_REGS_BASE + 0x2000)
 #define AR7_REGS_IRQ    (AR7_REGS_BASE + 0x2400)
 #define AR7_REGS_MAC1   (AR7_REGS_BASE + 0x2800)
 
+#define AR7_REGS_WDT    (AR7_REGS_BASE + 0x1f00)
+#define UR8_REGS_WDT    (AR7_REGS_BASE + 0x0b00)
+#define UR8_REGS_UART1  (AR7_REGS_BASE + 0x0f00)
+
 #define  AR7_RESET_PEREPHERIAL 0x0
 #define  AR7_RESET_SOFTWARE    0x4
 #define  AR7_RESET_STATUS      0x8
 
-#define AR7_RESET_BIT_MDIO   22
+#define AR7_RESET_BIT_CPMAC_LO 17
+#define AR7_RESET_BIT_CPMAC_HI 21
+#define AR7_RESET_BIT_MDIO     22
+#define AR7_RESET_BIT_EPHY     26
 
 /* GPIO control registers */
 #define  AR7_GPIO_INPUT  0x0
@@ -60,8 +58,6 @@
 #define  AR7_GPIO_DIR    0x8
 #define  AR7_GPIO_ENABLE 0xC
 
-#define AR7_GPIO_BIT_STATUS_LED   8
-
 #define AR7_CHIP_7100 0x18
 #define AR7_CHIP_7200 0x2b
 #define AR7_CHIP_7300 0x05
@@ -82,8 +78,6 @@ struct plat_dsl_data {
        int reset_bit_sar;
 };
 
-extern char *prom_getenv(char *envname);
-
 extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
 
 static inline u16 ar7_chip_id(void)
@@ -129,6 +123,7 @@ static inline int ar7_has_high_cpmac(void)
        }
 }
 #define ar7_has_high_vlynq ar7_has_high_cpmac
+#define ar7_has_second_uart ar7_has_high_cpmac
 
 static inline void ar7_device_enable(u32 bit)
 {
@@ -164,4 +159,4 @@ static inline void ar7_device_off(u32 bit)
        mdelay(20);
 }
 
-#endif
+#endif /* __AR7_H__ */