---- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
-+++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
-@@ -908,12 +908,15 @@ static bool ar9003_hw_rtt_restore(struct
- int i;
- bool restore;
-
-- if (!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT) || !ah->caldata)
-+ if (!ah->caldata)
- return false;
-
- hist = &ah->caldata->rtt_hist;
-+ if (!hist->num_readings)
-+ return false;
-+
- ar9003_hw_rtt_enable(ah);
-- ar9003_hw_rtt_set_mask(ah, 0x10);
-+ ar9003_hw_rtt_set_mask(ah, 0x00);
- for (i = 0; i < AR9300_MAX_CHAINS; i++) {
- if (!(ah->rxchainmask & (1 << i)))
- continue;
-@@ -1070,6 +1073,7 @@ skip_tx_iqcal:
- if (is_reusable && (hist->num_readings < RTT_HIST_MAX)) {
- u32 *table;
-
-+ hist->num_readings++;
- for (i = 0; i < AR9300_MAX_CHAINS; i++) {
- if (!(ah->rxchainmask & (1 << i)))
- continue;
---- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
-+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
-@@ -572,14 +572,14 @@
-
- #define AR_PHY_TXGAIN_TABLE (AR_SM_BASE + 0x300)
-
--#define AR_PHY_TX_IQCAL_CONTROL_0 (AR_SM_BASE + AR_SREV_9485(ah) ? \
-- 0x3c4 : 0x444)
--#define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + AR_SREV_9485(ah) ? \
-- 0x3c8 : 0x448)
--#define AR_PHY_TX_IQCAL_START (AR_SM_BASE + AR_SREV_9485(ah) ? \
-- 0x3c4 : 0x440)
--#define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + AR_SREV_9485(ah) ? \
-- 0x3f0 : 0x48c)
-+#define AR_PHY_TX_IQCAL_CONTROL_0 (AR_SM_BASE + (AR_SREV_9485(ah) ? \
-+ 0x3c4 : 0x444))
-+#define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + (AR_SREV_9485(ah) ? \
-+ 0x3c8 : 0x448))
-+#define AR_PHY_TX_IQCAL_START (AR_SM_BASE + (AR_SREV_9485(ah) ? \
-+ 0x3c4 : 0x440))
-+#define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + (AR_SREV_9485(ah) ? \
-+ 0x3f0 : 0x48c))
- #define AR_PHY_TX_IQCAL_CORR_COEFF_B0(_i) (AR_SM_BASE + \
- (AR_SREV_9485(ah) ? \
- 0x3d0 : 0x450) + ((_i) << 2))
-@@ -931,10 +931,10 @@
- #define AR_PHY_AIC_SRAM_ADDR_B1 (AR_SM1_BASE + 0x5f0)
- #define AR_PHY_AIC_SRAM_DATA_B1 (AR_SM1_BASE + 0x5f4)
-
--#define AR_PHY_RTT_TABLE_SW_INTF_B(i) (0x384 + (i) ? \
-- AR_SM1_BASE : AR_SM_BASE)
--#define AR_PHY_RTT_TABLE_SW_INTF_1_B(i) (0x388 + (i) ? \
-- AR_SM1_BASE : AR_SM_BASE)
-+#define AR_PHY_RTT_TABLE_SW_INTF_B(i) (0x384 + ((i) ? \
-+ AR_SM1_BASE : AR_SM_BASE))
-+#define AR_PHY_RTT_TABLE_SW_INTF_1_B(i) (0x388 + ((i) ? \
-+ AR_SM1_BASE : AR_SM_BASE))
- /*
- * Channel 2 Register Map
- */