ar71xx: don't register PCI controller on AR934x if PCIE_RC bit is not set

[openwrt.git] / target / linux / lantiq / patches / 0026-MIPS-lantiq-adds-GPIO3-support-on-AR9.patch

diff --git a/target/linux/lantiq/patches/0026-MIPS-lantiq-adds-GPIO3-support-on-AR9.patch b/target/linux/lantiq/patches/0026-MIPS-lantiq-adds-GPIO3-support-on-AR9.patch
index e96d9b7..ee41b3a 100644 (file)
--- a/target/linux/lantiq/patches/0026-MIPS-lantiq-adds-GPIO3-support-on-AR9.patch
+++ b/target/linux/lantiq/patches/0026-MIPS-lantiq-adds-GPIO3-support-on-AR9.patch
@@ -20,7 +20,7 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
 
 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
 
 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h

-@@ -113,7 +113,9 @@
+@@ -121,7 +121,9 @@

  #define LTQ_GPIO0_BASE_ADDR   0x1E100B10
  #define LTQ_GPIO1_BASE_ADDR   0x1E100B40
  #define LTQ_GPIO2_BASE_ADDR   0x1E100B70
  #define LTQ_GPIO0_BASE_ADDR   0x1E100B10
  #define LTQ_GPIO1_BASE_ADDR   0x1E100B40
  #define LTQ_GPIO2_BASE_ADDR   0x1E100B70