[brcm63xx] add missing patch which fakes a cardbus controller on top of PCI, thanks...

[openwrt.git] / target / linux / brcm63xx / files / arch / mips / bcm63xx / cpu.c

diff --git a/target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c b/target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c
index c6f7fad..00da282 100644 (file)
--- a/target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c
+++ b/target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c
@@ -88,19 +88,38 @@ static const unsigned long bcm96338_regs_spi[] = {
  */
 
 static const unsigned long bcm96345_regs_base[] = {
  */
 
 static const unsigned long bcm96345_regs_base[] = {

+       [RSET_DSL_LMEM]         = BCM_6345_DSL_LMEM_BASE,

        [RSET_PERF]             = BCM_6345_PERF_BASE,
        [RSET_TIMER]            = BCM_6345_TIMER_BASE,
        [RSET_WDT]              = BCM_6345_WDT_BASE,
        [RSET_UART0]            = BCM_6345_UART0_BASE,
        [RSET_GPIO]             = BCM_6345_GPIO_BASE,
        [RSET_PERF]             = BCM_6345_PERF_BASE,
        [RSET_TIMER]            = BCM_6345_TIMER_BASE,
        [RSET_WDT]              = BCM_6345_WDT_BASE,
        [RSET_UART0]            = BCM_6345_UART0_BASE,
        [RSET_GPIO]             = BCM_6345_GPIO_BASE,

+       [RSET_SPI]              = BCM_6345_SPI_BASE,
+       [RSET_UDC0]             = BCM_6345_UDC0_BASE,
+       [RSET_OHCI0]            = BCM_6345_OHCI0_BASE,
+       [RSET_OHCI_PRIV]        = BCM_6345_OHCI_PRIV_BASE,
+       [RSET_USBH_PRIV]        = BCM_6345_USBH_PRIV_BASE,
+       [RSET_MPI]              = BCM_6345_MPI_BASE,
+       [RSET_PCMCIA]           = BCM_6345_PCMCIA_BASE,
+       [RSET_DSL]              = BCM_6345_DSL_BASE,
+       [RSET_ENET0]            = BCM_6345_ENET0_BASE,
+       [RSET_ENET1]            = BCM_6345_ENET1_BASE,
+       [RSET_ENETDMA]          = BCM_6345_ENETDMA_BASE,
+       [RSET_EHCI0]            = BCM_6345_EHCI0_BASE,
+       [RSET_SDRAM]            = BCM_6345_SDRAM_BASE,
+       [RSET_MEMC]             = BCM_6345_MEMC_BASE,
+       [RSET_DDR]              = BCM_6345_DDR_BASE,

 };
 
 static const int bcm96345_irqs[] = {
        [IRQ_TIMER]             = BCM_6345_TIMER_IRQ,
        [IRQ_UART0]             = BCM_6345_UART0_IRQ,
        [IRQ_DSL]               = BCM_6345_DSL_IRQ,
 };
 
 static const int bcm96345_irqs[] = {
        [IRQ_TIMER]             = BCM_6345_TIMER_IRQ,
        [IRQ_UART0]             = BCM_6345_UART0_IRQ,
        [IRQ_DSL]               = BCM_6345_DSL_IRQ,

+       [IRQ_UDC0]              = BCM_6345_UDC0_IRQ,

        [IRQ_ENET0]             = BCM_6345_ENET0_IRQ,
        [IRQ_ENET_PHY]          = BCM_6345_ENET_PHY_IRQ,
        [IRQ_ENET0]             = BCM_6345_ENET0_IRQ,
        [IRQ_ENET_PHY]          = BCM_6345_ENET_PHY_IRQ,

+       [IRQ_ENET0_RXDMA]       = BCM_6345_ENET0_RXDMA_IRQ,
+       [IRQ_ENET0_TXDMA]       = BCM_6345_ENET0_TXDMA_IRQ,

 };
 
 /*
 };
 
 /*