omap24xx: bump to 3.1.3

[openwrt.git] / target / linux / ramips / files / drivers / net / ramips_esw.c

diff --git a/target/linux/ramips/files/drivers/net/ramips_esw.c b/target/linux/ramips/files/drivers/net/ramips_esw.c
index 7aa5fd1..c681eed 100644 (file)
--- a/target/linux/ramips/files/drivers/net/ramips_esw.c
+++ b/target/linux/ramips/files/drivers/net/ramips_esw.c
@@ -5,7 +5,7 @@
 
 #define RT305X_ESW_REG_FCT0            0x08
 #define RT305X_ESW_REG_PFC1            0x14
-#define RT305X_ESW_REG_PVIDC(_n)       (0x48 + 4 * (_n))
+#define RT305X_ESW_REG_PVIDC(_n)       (0x40 + 4 * (_n))
 #define RT305X_ESW_REG_VLANI(_n)       (0x50 + 4 * (_n))
 #define RT305X_ESW_REG_VMSC(_n)                (0x70 + 4 * (_n))
 #define RT305X_ESW_REG_FPA             0x84
@@ -37,6 +37,20 @@
 #define RT305X_ESW_VMSC_MSC_M          0xff
 #define RT305X_ESW_VMSC_MSC_S          8
 
+#define RT305X_ESW_SOCPC_DISUN2CPU_S   0
+#define RT305X_ESW_SOCPC_DISMC2CPU_S   8
+#define RT305X_ESW_SOCPC_DISBC2CPU_S   16
+#define RT305X_ESW_SOCPC_CRC_PADDING   BIT(25)
+
+#define RT305X_ESW_POC1_EN_BP_S                0
+#define RT305X_ESW_POC1_EN_FC_S                8
+#define RT305X_ESW_POC1_DIS_RMC2CPU_S  16
+#define RT305X_ESW_POC1_DIS_PORT_S     23
+
+#define RT305X_ESW_POC3_UNTAG_EN_S     0
+#define RT305X_ESW_POC3_ENAGING_S      8
+#define RT305X_ESW_POC3_DIS_UC_PAUSE_S 16
+
 #define RT305X_ESW_PORT0               0
 #define RT305X_ESW_PORT1               1
 #define RT305X_ESW_PORT2               2
@@ -45,6 +59,22 @@
 #define RT305X_ESW_PORT5               5
 #define RT305X_ESW_PORT6               6
 
+#define RT305X_ESW_PORTS_INTERNAL                                      \
+               (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |        \
+                BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |        \
+                BIT(RT305X_ESW_PORT4))
+
+#define RT305X_ESW_PORTS_NOCPU \
+               (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
+
+#define RT305X_ESW_PORTS_CPU   BIT(RT305X_ESW_PORT6)
+
+#define RT305X_ESW_PORTS_ALL   \
+               (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
+
+#define RT305X_ESW_NUM_VLANS   16
+#define RT305X_ESW_NUM_PORTS   7
+
 struct rt305x_esw {
        void __iomem *base;
        struct rt305x_esw_platform_data *pdata;
@@ -145,7 +175,7 @@ rt305x_esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
        s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
        rt305x_esw_rmw(esw,
                       RT305X_ESW_REG_PVIDC(port / 2),
-                      RT305X_ESW_PVIDC_PVID_S << s,
+                      RT305X_ESW_PVIDC_PVID_M << s,
                       (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
 }
 
@@ -170,13 +200,30 @@ rt305x_esw_hw_init(struct rt305x_esw *esw)
        rt305x_esw_wr(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
        rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_SGC2);
        rt305x_esw_wr(esw, 0x00405555, RT305X_ESW_REG_PFC1);
-       rt305x_esw_wr(esw, 0x00007f7f, RT305X_ESW_REG_POC1);
-       rt305x_esw_wr(esw, 0x00007f3f, RT305X_ESW_REG_POC3);
+
+       /* Enable Back Pressure, and Flow Control */
+       rt305x_esw_wr(esw,
+                     ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC1_EN_BP_S) |
+                      (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC1_EN_FC_S)),
+                     RT305X_ESW_REG_POC1);
+
+       /* Enable Aging, and VLAN TAG removal */
+       rt305x_esw_wr(esw,
+                     ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC3_ENAGING_S) |
+                      (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC3_UNTAG_EN_S)),
+                     RT305X_ESW_REG_POC3);
+
        rt305x_esw_wr(esw, 0x00d6500c, RT305X_ESW_REG_FCT2);
        rt305x_esw_wr(esw, 0x0008a301, RT305X_ESW_REG_SGC);
-       rt305x_esw_wr(esw, 0x02404040, RT305X_ESW_REG_SOCPC);
-       rt305x_esw_set_pvid(esw, RT305X_ESW_PORT4, 2);
-       rt305x_esw_set_pvid(esw, RT305X_ESW_PORT5, 1);
+
+       /* Setup SoC Port control register */
+       rt305x_esw_wr(esw,
+                     (RT305X_ESW_SOCPC_CRC_PADDING |
+                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
+                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
+                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
+                     RT305X_ESW_REG_SOCPC);
+
        rt305x_esw_wr(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
        rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_FPA);
 
@@ -206,17 +253,47 @@ rt305x_esw_hw_init(struct rt305x_esw *esw)
        /* select local register */
        rt305x_mii_write(esw, 0, 31, 0x8000);
 
-       /* set default vlan */
-       rt305x_esw_set_vlan_id(esw, 0, 1);
-       rt305x_esw_set_vlan_id(esw, 1, 2);
-       rt305x_esw_set_vmsc(esw, 0,
-                           (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |
-                            BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |
-                            BIT(RT305X_ESW_PORT6)));
-       rt305x_esw_set_vmsc(esw, 1,
-                           (BIT(RT305X_ESW_PORT4) | BIT(RT305X_ESW_PORT6)));
-       rt305x_esw_set_vmsc(esw, 2, 0);
-       rt305x_esw_set_vmsc(esw, 3, 0);
+       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
+               rt305x_esw_set_vlan_id(esw, i, 0);
+               rt305x_esw_set_vmsc(esw, i, 0);
+       }
+
+       for (i = 0; i < RT305X_ESW_NUM_PORTS; i++)
+               rt305x_esw_set_pvid(esw, i, 1);
+
+       switch (esw->pdata->vlan_config) {
+       case RT305X_ESW_VLAN_CONFIG_NONE:
+               break;
+
+       case RT305X_ESW_VLAN_CONFIG_LLLLW:
+               rt305x_esw_set_vlan_id(esw, 0, 1);
+               rt305x_esw_set_vlan_id(esw, 1, 2);
+               rt305x_esw_set_pvid(esw, RT305X_ESW_PORT4, 2);
+
+               rt305x_esw_set_vmsc(esw, 0,
+                               BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |
+                               BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |
+                               BIT(RT305X_ESW_PORT6));
+               rt305x_esw_set_vmsc(esw, 1,
+                               BIT(RT305X_ESW_PORT4) | BIT(RT305X_ESW_PORT6));
+               break;
+
+       case RT305X_ESW_VLAN_CONFIG_WLLLL:
+               rt305x_esw_set_vlan_id(esw, 0, 1);
+               rt305x_esw_set_vlan_id(esw, 1, 2);
+               rt305x_esw_set_pvid(esw, RT305X_ESW_PORT0, 2);
+
+               rt305x_esw_set_vmsc(esw, 0,
+                               BIT(RT305X_ESW_PORT1) | BIT(RT305X_ESW_PORT2) |
+                               BIT(RT305X_ESW_PORT3) | BIT(RT305X_ESW_PORT4) |
+                               BIT(RT305X_ESW_PORT6));
+               rt305x_esw_set_vmsc(esw, 1,
+                               BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT6));
+               break;
+
+       default:
+               BUG();
+       }
 }
 
 static int
@@ -293,7 +370,7 @@ rt305x_esw_init(void)
        return platform_driver_register(&rt305x_esw_driver);
 }
 
-static void __exit
+static void
 rt305x_esw_exit(void)
 {
        platform_driver_unregister(&rt305x_esw_driver);