[ar71xx] define some bits of the ethernet controller's registers

[openwrt.git] / target / linux / atheros / patches-2.6.27 / 902-mips_clocksource_init_war.patch

diff --git a/target/linux/atheros/patches-2.6.27/902-mips_clocksource_init_war.patch b/target/linux/atheros/patches-2.6.27/902-mips_clocksource_init_war.patch
index 564321c..03a66ff 100644 (file)
--- a/target/linux/atheros/patches-2.6.27/902-mips_clocksource_init_war.patch
+++ b/target/linux/atheros/patches-2.6.27/902-mips_clocksource_init_war.patch
@@ -23,7 +23,7 @@
   * The SMTC Kernel for the 34K, 1004K, et. al. replaces several
   * of these routines with SMTC-specific variants.
   */
-@@ -30,6 +46,7 @@
+@@ -30,6 +46,7 @@ static int mips_next_event(unsigned long
        cnt = read_c0_count();
        cnt += delta;
        write_c0_compare(cnt);
@@ -31,7 +31,7 @@
        res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
        return res;
  }
-@@ -99,22 +116,6 @@
+@@ -99,22 +116,6 @@ static int c0_compare_int_pending(void)
        return (read_c0_cause() >> cp0_compare_irq) & 0x100;
  }