[PATCH] Fix permissions for /etc and other dirs after clean flash (#6039)

[openwrt.git] / package / uboot-lantiq / files / board / infineon / easy50712 / ddr_settings.h

diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h
index cecd279..3a4b135 100644 (file)
--- a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h
+++ b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h
@@ -1,50 +1,50 @@
-/* Settings for Denali DDR SDRAM controller */\r
-/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */\r
-#define MC_DC0_VALUE   0x1B1B\r
-#define MC_DC1_VALUE   0x0\r
-#define MC_DC2_VALUE   0x0\r
-#define MC_DC3_VALUE   0x0\r
-#define MC_DC4_VALUE   0x0\r
-#define MC_DC5_VALUE   0x200\r
-#define MC_DC6_VALUE   0x605\r
-#define MC_DC7_VALUE   0x303\r
-#define MC_DC8_VALUE   0x102\r
-#define MC_DC9_VALUE   0x70a\r
-#define MC_DC10_VALUE  0x203\r
-#define MC_DC11_VALUE  0xc02\r
-#define MC_DC12_VALUE  0x1C8\r
-#define MC_DC13_VALUE  0x1\r
-#define MC_DC14_VALUE  0x0\r
-#define MC_DC15_VALUE  0xf3c\r
-#define MC_DC16_VALUE  0xC800\r
-#define MC_DC17_VALUE  0xd\r
-#define MC_DC18_VALUE  0x300\r
-#define MC_DC19_VALUE  0x200\r
-#define MC_DC20_VALUE  0xA03\r
-#define MC_DC21_VALUE  0x1d00\r
-#define MC_DC22_VALUE  0x1d1d\r
-#define MC_DC23_VALUE  0x0\r
-#define MC_DC24_VALUE  0x5e   /* was 0x7f */\r
-#define MC_DC25_VALUE  0x0\r
-#define MC_DC26_VALUE  0x0\r
-#define MC_DC27_VALUE  0x0\r
-#define MC_DC28_VALUE  0x510\r
-#define MC_DC29_VALUE  0x2d89\r
-#define MC_DC30_VALUE  0x8300\r
-#define MC_DC31_VALUE  0x0\r
-#define MC_DC32_VALUE  0x0\r
-#define MC_DC33_VALUE  0x0\r
-#define MC_DC34_VALUE  0x0\r
-#define MC_DC35_VALUE  0x0\r
-#define MC_DC36_VALUE  0x0\r
-#define MC_DC37_VALUE  0x0\r
-#define MC_DC38_VALUE  0x0\r
-#define MC_DC39_VALUE  0x0\r
-#define MC_DC40_VALUE  0x0\r
-#define MC_DC41_VALUE  0x0\r
-#define MC_DC42_VALUE  0x0\r
-#define MC_DC43_VALUE  0x0\r
-#define MC_DC44_VALUE  0x0\r
-#define MC_DC45_VALUE  0x500\r
-//#define MC_DC45_VALUE        0x400\r
-#define MC_DC46_VALUE  0x0\r
+/* Settings for Denali DDR SDRAM controller */
+/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */
+#define MC_DC0_VALUE   0x1B1B
+#define MC_DC1_VALUE   0x0
+#define MC_DC2_VALUE   0x0
+#define MC_DC3_VALUE   0x0
+#define MC_DC4_VALUE   0x0
+#define MC_DC5_VALUE   0x200
+#define MC_DC6_VALUE   0x605
+#define MC_DC7_VALUE   0x303
+#define MC_DC8_VALUE   0x102
+#define MC_DC9_VALUE   0x70a
+#define MC_DC10_VALUE  0x203
+#define MC_DC11_VALUE  0xc02
+#define MC_DC12_VALUE  0x1C8
+#define MC_DC13_VALUE  0x1
+#define MC_DC14_VALUE  0x0
+#define MC_DC15_VALUE  0xf3c
+#define MC_DC16_VALUE  0xC800
+#define MC_DC17_VALUE  0xd
+#define MC_DC18_VALUE  0x300
+#define MC_DC19_VALUE  0x200
+#define MC_DC20_VALUE  0xA03
+#define MC_DC21_VALUE  0x1d00
+#define MC_DC22_VALUE  0x1d1d
+#define MC_DC23_VALUE  0x0
+#define MC_DC24_VALUE  0x5e   /* was 0x7f */
+#define MC_DC25_VALUE  0x0
+#define MC_DC26_VALUE  0x0
+#define MC_DC27_VALUE  0x0
+#define MC_DC28_VALUE  0x510
+#define MC_DC29_VALUE  0x2d89
+#define MC_DC30_VALUE  0x8300
+#define MC_DC31_VALUE  0x0
+#define MC_DC32_VALUE  0x0
+#define MC_DC33_VALUE  0x0
+#define MC_DC34_VALUE  0x0
+#define MC_DC35_VALUE  0x0
+#define MC_DC36_VALUE  0x0
+#define MC_DC37_VALUE  0x0
+#define MC_DC38_VALUE  0x0
+#define MC_DC39_VALUE  0x0
+#define MC_DC40_VALUE  0x0
+#define MC_DC41_VALUE  0x0
+#define MC_DC42_VALUE  0x0
+#define MC_DC43_VALUE  0x0
+#define MC_DC44_VALUE  0x0
+#define MC_DC45_VALUE  0x500
+//#define MC_DC45_VALUE        0x400
+#define MC_DC46_VALUE  0x0