* WAR for BAR issue - We are unable to access the PCI device space
* if we set the BAR with proper base address
*/
- if ((where == 0x10) && (size == 4))
- ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0xffff);
+ if ((where == 0x10) && (size == 4)) {
+ u32 val;
+ val = (ar71xx_soc == AR71XX_SOC_AR7240) ? 0xffff : 0x1000ffff;
+ ar724x_pci_write(ar724x_pci_devcfg_base, where, size, val);
+ }
return PCIBIOS_SUCCESSFUL;
}
udelay(100000);
}
- __raw_writel(AR724X_PCI_APP_LTSSM_ENABLE, base + AR724X_PCI_REG_APP);
+ if (ar71xx_soc == AR71XX_SOC_AR7240)
+ t = AR724X_PCI_APP_LTSSM_ENABLE;
+ else
+ t = 0x1ffc1;
+ __raw_writel(t, base + AR724X_PCI_REG_APP);
/* flush write */
(void) __raw_readl(base + AR724X_PCI_REG_APP);
udelay(1000);
return -ENODEV;
}
- if (ar71xx_soc == AR71XX_SOC_AR7241 || ar71xx_soc == AR71XX_SOC_AR7242) {
+ if (ar71xx_soc == AR71XX_SOC_AR7241 ||
+ ar71xx_soc == AR71XX_SOC_AR7242) {
t = __raw_readl(base + AR724X_PCI_REG_APP);
t |= BIT(16);
__raw_writel(t, base + AR724X_PCI_REG_APP);
return 0;
- err_unmap_ctrl:
+err_unmap_ctrl:
iounmap(ar724x_pci_ctrl_base);
- err_unmap_devcfg:
+err_unmap_devcfg:
iounmap(ar724x_pci_devcfg_base);
- err_unmap_localcfg:
+err_unmap_localcfg:
iounmap(ar724x_pci_localcfg_base);
- err:
+err:
return ret;
}