X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/07244cdc4fa4c87351dffbdaae4cbd131edf43ef..59f0b5d7218274f52c546fbf61d3e6c30472632d:/target/linux/ramips/files/arch/mips/ralink/rt288x/setup.c

diff --git a/target/linux/ramips/files/arch/mips/ralink/rt288x/setup.c b/target/linux/ramips/files/arch/mips/ralink/rt288x/setup.c
index e2328fe5e..65e187d3a 100644
--- a/target/linux/ramips/files/arch/mips/ralink/rt288x/setup.c
+++ b/target/linux/ramips/files/arch/mips/ralink/rt288x/setup.c
@@ -14,6 +14,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/err.h>
+#include <linux/clk.h>
 
 #include <asm/mips_machine.h>
 #include <asm/reboot.h>
@@ -22,6 +24,7 @@
 #include <asm/mach-ralink/common.h>
 #include <asm/mach-ralink/rt288x.h>
 #include <asm/mach-ralink/rt288x_regs.h>
+#include "common.h"
 
 static void rt288x_restart(char *command)
 {
@@ -44,27 +47,43 @@ unsigned int __cpuinit get_c0_compare_irq(void)
 
 void __init ramips_soc_setup(void)
 {
+	struct clk *clk;
+
 	rt288x_sysc_base = ioremap_nocache(RT2880_SYSC_BASE, RT2880_SYSC_SIZE);
 	rt288x_memc_base = ioremap_nocache(RT2880_MEMC_BASE, RT2880_MEMC_SIZE);
 
 	rt288x_detect_sys_type();
-	rt288x_detect_sys_freq();
+	rt288x_clocks_init();
+
+	clk = clk_get(NULL, "cpu");
+	if (IS_ERR(clk))
+		panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
 
 	printk(KERN_INFO "%s running at %lu.%02lu MHz\n", ramips_sys_type,
-		rt288x_cpu_freq / 1000000,
-		(rt288x_cpu_freq % 1000000) * 100 / 1000000);
+		clk_get_rate(clk) / 1000000,
+		(clk_get_rate(clk) % 1000000) * 100 / 1000000);
 
 	_machine_restart = rt288x_restart;
 	_machine_halt = rt288x_halt;
 	pm_power_off = rt288x_halt;
 
-	ramips_early_serial_setup(0, RT2880_UART0_BASE, rt288x_sys_freq,
+	clk = clk_get(NULL, "uart");
+	if (IS_ERR(clk))
+		panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
+
+	ramips_early_serial_setup(0, RT2880_UART0_BASE, clk_get_rate(clk),
 				  RT2880_INTC_IRQ_UART0);
-	ramips_early_serial_setup(1, RT2880_UART1_BASE, rt288x_sys_freq,
+	ramips_early_serial_setup(1, RT2880_UART1_BASE, clk_get_rate(clk),
 				  RT2880_INTC_IRQ_UART1);
 }
 
 void __init plat_time_init(void)
 {
-	mips_hpt_frequency = rt288x_cpu_freq / 2;
+	struct clk *clk;
+
+	clk = clk_get(NULL, "cpu");
+	if (IS_ERR(clk))
+		panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
+
+	mips_hpt_frequency = clk_get_rate(clk) / 2;
 }