X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/1a03e70f1670e914db99349b33e564be7c3a2caa..ea714ecea24591aead112b59e27e630f088d3dc4:/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c diff --git a/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c b/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c index dc4aa4837..e29741901 100644 --- a/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c +++ b/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c @@ -4,27 +4,40 @@ #include #include +#include #define RT2880_PCI_SLOT1_BASE 0x20000000 -#define RALINK_PCI_BASE 0xA0440000 -#define RT2880_PCI_PCICFG_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0000)) -#define RT2880_PCI_ARBCTL ((unsigned long*)(RALINK_PCI_BASE + 0x0080)) -#define RT2880_PCI_BAR0SETUP_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0010)) -#define RT2880_PCI_CONFIG_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0020)) -#define RT2880_PCI_CONFIG_DATA ((unsigned long*)(RALINK_PCI_BASE + 0x0024)) -#define RT2880_PCI_MEMBASE ((unsigned long*)(RALINK_PCI_BASE + 0x0028)) -#define RT2880_PCI_IOBASE ((unsigned long*)(RALINK_PCI_BASE + 0x002C)) -#define RT2880_PCI_IMBASEBAR0_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0018)) -#define RT2880_PCI_ID ((unsigned long*)(RALINK_PCI_BASE + 0x0030)) -#define RT2880_PCI_CLASS ((unsigned long*)(RALINK_PCI_BASE + 0x0034)) -#define RT2880_PCI_SUBID ((unsigned long*)(RALINK_PCI_BASE + 0x0038)) -#define RT2880_PCI_PCIMSK_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x000C)) + +#define RT2880_PCI_REG_PCICFG_ADDR 0x00 +#define RT2880_PCI_REG_PCIMSK_ADDR 0x0c +#define RT2880_PCI_REG_BAR0SETUP_ADDR 0x10 +#define RT2880_PCI_REG_IMBASEBAR0_ADDR 0x18 +#define RT2880_PCI_REG_CONFIG_ADDR 0x20 +#define RT2880_PCI_REG_CONFIG_DATA 0x24 +#define RT2880_PCI_REG_MEMBASE 0x28 +#define RT2880_PCI_REG_IOBASE 0x2c +#define RT2880_PCI_REG_ID 0x30 +#define RT2880_PCI_REG_CLASS 0x34 +#define RT2880_PCI_REG_SUBID 0x38 +#define RT2880_PCI_REG_ARBCTL 0x80 #define PCI_ACCESS_READ 0 #define PCI_ACCESS_WRITE 1 -static int config_access(unsigned char access_type, struct pci_bus *bus, - unsigned int devfn, unsigned char where, u32 *data) +void __iomem *rt2880_pci_base; + +static u32 rt2880_pci_reg_read(u32 reg) +{ + return readl(rt2880_pci_base + reg); +} + +static void rt2880_pci_reg_write(u32 val, u32 reg) +{ + writel(val, rt2880_pci_base + reg); +} + +static void config_access(unsigned char access_type, struct pci_bus *bus, + unsigned int devfn, unsigned char where, u32 *data) { unsigned int slot = PCI_SLOT(devfn); unsigned int address; @@ -33,22 +46,19 @@ static int config_access(unsigned char access_type, struct pci_bus *bus, address = (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000; - writel(address, RT2880_PCI_CONFIG_ADDR); + rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); if (access_type == PCI_ACCESS_WRITE) - writel(*data, RT2880_PCI_CONFIG_DATA); + rt2880_pci_reg_write(*data, RT2880_PCI_REG_CONFIG_DATA); else - *data = readl(RT2880_PCI_CONFIG_DATA); - - return 0; + *data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA); } -int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 *val) +static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) { u32 data = 0; - if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) - return PCIBIOS_DEVICE_NOT_FOUND; + config_access(PCI_ACCESS_READ, bus, devfn, where, &data); if (size == 1) *val = (data >> ((where & 3) << 3)) & 0xff; @@ -60,16 +70,15 @@ int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, return PCIBIOS_SUCCESSFUL; } -int pci_config_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) +static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) { u32 data = 0; if (size == 4) { data = val; } else { - if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) - return PCIBIOS_DEVICE_NOT_FOUND; + config_access(PCI_ACCESS_READ, bus, devfn, where, &data); if (size == 1) data = (data & ~(0xff << ((where & 3) << 3))) | (val << ((where & 3) << 3)); @@ -78,37 +87,34 @@ int pci_config_write(struct pci_bus *bus, unsigned int devfn, (val << ((where & 3) << 3)); } - if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) - return PCIBIOS_DEVICE_NOT_FOUND; + config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data); return PCIBIOS_SUCCESSFUL; } -struct pci_ops rt2880_pci_ops = { - .read = pci_config_read, - .write = pci_config_write, +static struct pci_ops rt2880_pci_ops = { + .read = rt2880_pci_config_read, + .write = rt2880_pci_config_write, }; -static struct resource pci_io_resource = { - .name = "pci MEM space", +static struct resource rt2880_pci_io_resource = { + .name = "PCI MEM space", .start = 0x20000000, .end = 0x2FFFFFFF, .flags = IORESOURCE_MEM, }; -static struct resource pci_mem_resource = { - .name = "pci IO space", +static struct resource rt2880_pci_mem_resource = { + .name = "PCI IO space", .start = 0x00460000, .end = 0x0046FFFF, .flags = IORESOURCE_IO, }; -struct pci_controller rt2880_controller = { +static struct pci_controller rt2880_pci_controller = { .pci_ops = &rt2880_pci_ops, - .mem_resource = &pci_io_resource, - .io_resource = &pci_mem_resource, - .mem_offset = 0x00000000UL, - .io_offset = 0x00000000UL, + .mem_resource = &rt2880_pci_io_resource, + .io_resource = &rt2880_pci_mem_resource, }; void inline read_config(unsigned long bus, unsigned long dev, @@ -119,8 +125,8 @@ void inline read_config(unsigned long bus, unsigned long dev, address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000; - writel(address, RT2880_PCI_CONFIG_ADDR); - *val = readl(RT2880_PCI_CONFIG_DATA); + rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); + *val = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA); } void inline write_config(unsigned long bus, unsigned long dev, @@ -131,8 +137,8 @@ void inline write_config(unsigned long bus, unsigned long dev, address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000; - writel(address, RT2880_PCI_CONFIG_ADDR); - writel(val, RT2880_PCI_CONFIG_DATA); + rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); + rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA); } int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) @@ -171,27 +177,29 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq; } -int init_rt2880pci(void) +static int __init rt2880_pci_init(void) { unsigned long val = 0; int i; - writel(0, RT2880_PCI_PCICFG_ADDR); + rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE); + + rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR); for(i = 0; i < 0xfffff; i++) {} - writel(0x79, RT2880_PCI_ARBCTL); - writel(0x07FF0001, RT2880_PCI_BAR0SETUP_ADDR); - writel(RT2880_PCI_SLOT1_BASE, RT2880_PCI_MEMBASE); - writel(0x00460000, RT2880_PCI_IOBASE); - writel(0x08000000, RT2880_PCI_IMBASEBAR0_ADDR); - writel(0x08021814, RT2880_PCI_ID); - writel(0x00800001, RT2880_PCI_CLASS); - writel(0x28801814, RT2880_PCI_SUBID); - writel(0x000c0000, RT2880_PCI_PCIMSK_ADDR); + rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL); + rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR); + rt2880_pci_reg_write(RT2880_PCI_SLOT1_BASE, RT2880_PCI_REG_MEMBASE); + rt2880_pci_reg_write(0x00460000, RT2880_PCI_REG_IOBASE); + rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR); + rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID); + rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS); + rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID); + rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR); write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000); read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val); - register_pci_controller(&rt2880_controller); + register_pci_controller(&rt2880_pci_controller); return 0; } @@ -204,4 +212,4 @@ struct pci_fixup pcibios_fixups[] = { {0} }; -arch_initcall(init_rt2880pci); +arch_initcall(rt2880_pci_init);