X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/1ee264d2d6960eb09c580554424c17a7c52a1ea1..1493a33c1bb34526dbcd975f2112af3af9580ff9:/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c diff --git a/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c b/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c index 8ec50d6e4..14b7d42ba 100644 --- a/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c +++ b/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c @@ -19,7 +19,10 @@ #include #include -#define RT2880_PCI_SLOT1_BASE 0x20000000 +#define RT2880_PCI_MEM_BASE 0x20000000 +#define RT2880_PCI_MEM_SIZE 0x10000000 +#define RT2880_PCI_IO_BASE 0x00460000 +#define RT2880_PCI_IO_SIZE 0x00010000 #define RT2880_PCI_REG_PCICFG_ADDR 0x00 #define RT2880_PCI_REG_PCIMSK_ADDR 0x0c @@ -37,7 +40,8 @@ #define PCI_ACCESS_READ 0 #define PCI_ACCESS_WRITE 1 -void __iomem *rt2880_pci_base; +static void __iomem *rt2880_pci_base; +static DEFINE_SPINLOCK(rt2880_pci_lock); static u32 rt2880_pci_reg_read(u32 reg) { @@ -49,15 +53,20 @@ static void rt2880_pci_reg_write(u32 val, u32 reg) writel(val, rt2880_pci_base + reg); } +static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot, + unsigned int func, unsigned int where) +{ + return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | + 0x80000000); +} + static void config_access(unsigned char access_type, struct pci_bus *bus, unsigned int devfn, unsigned char where, u32 *data) { - unsigned int slot = PCI_SLOT(devfn); unsigned int address; - u8 func = PCI_FUNC(devfn); - address = (bus->number << 16) | (slot << 11) | (func << 8) | - (where & 0xfc) | 0x80000000; + address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), + PCI_FUNC(devfn), where); rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); if (access_type == PCI_ACCESS_WRITE) @@ -69,16 +78,24 @@ static void config_access(unsigned char access_type, struct pci_bus *bus, static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) { + unsigned long flags; u32 data = 0; + spin_lock_irqsave(&rt2880_pci_lock, flags); config_access(PCI_ACCESS_READ, bus, devfn, where, &data); + spin_unlock_irqrestore(&rt2880_pci_lock, flags); - if (size == 1) + switch (size) { + case 1: *val = (data >> ((where & 3) << 3)) & 0xff; - else if (size == 2) + break; + case 2: *val = (data >> ((where & 3) << 3)) & 0xffff; - else + break; + case 4: *val = data; + break; + } return PCIBIOS_SUCCESSFUL; } @@ -86,21 +103,29 @@ static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn, static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) { + unsigned long flags; u32 data = 0; - if (size == 4) { - data = val; - } else { + spin_lock_irqsave(&rt2880_pci_lock, flags); + + switch (size) { + case 1: + config_access(PCI_ACCESS_READ, bus, devfn, where, &data); + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + break; + case 2: config_access(PCI_ACCESS_READ, bus, devfn, where, &data); - if (size == 1) - data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - else if (size == 2) - data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + break; + case 4: + data = val; + break; } config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data); + spin_unlock_irqrestore(&rt2880_pci_lock, flags); return PCIBIOS_SUCCESSFUL; } @@ -112,15 +137,15 @@ static struct pci_ops rt2880_pci_ops = { static struct resource rt2880_pci_io_resource = { .name = "PCI MEM space", - .start = 0x20000000, - .end = 0x2FFFFFFF, + .start = RT2880_PCI_MEM_BASE, + .end = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1, .flags = IORESOURCE_MEM, }; static struct resource rt2880_pci_mem_resource = { .name = "PCI IO space", - .start = 0x00460000, - .end = 0x0046FFFF, + .start = RT2880_PCI_IO_BASE, + .end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1, .flags = IORESOURCE_IO, }; @@ -135,11 +160,14 @@ static inline void read_config(unsigned long bus, unsigned long dev, unsigned long *val) { unsigned long address; + unsigned long flags; - address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | - 0x80000000; + address = rt2880_pci_get_cfgaddr(bus, dev, func, reg); + + spin_lock_irqsave(&rt2880_pci_lock, flags); rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); *val = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA); + spin_unlock_irqrestore(&rt2880_pci_lock, flags); } static inline void write_config(unsigned long bus, unsigned long dev, @@ -147,11 +175,14 @@ static inline void write_config(unsigned long bus, unsigned long dev, unsigned long val) { unsigned long address; + unsigned long flags; + + address = rt2880_pci_get_cfgaddr(bus, dev, func, reg); - address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | - 0x80000000; + spin_lock_irqsave(&rt2880_pci_lock, flags); rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA); + spin_unlock_irqrestore(&rt2880_pci_lock, flags); } int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) @@ -202,8 +233,8 @@ static int __init rt2880_pci_init(void) rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL); rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR); - rt2880_pci_reg_write(RT2880_PCI_SLOT1_BASE, RT2880_PCI_REG_MEMBASE); - rt2880_pci_reg_write(0x00460000, RT2880_PCI_REG_IOBASE); + rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE); + rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE); rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR); rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID); rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);