X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/25c15c7d1f72fc6c0e6027f161b137a4b2da79b8..f00dfe552e907d41bff7da4d873ae9760bab32f3:/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c diff --git a/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c b/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c index e3b05d061..2fccd7bb7 100644 --- a/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c +++ b/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c @@ -1,3 +1,16 @@ +/* + * Ralink RT288x SoC PCI register definitions + * + * Copyright (C) 2009 John Crispin + * Copyright (C) 2009 Gabor Juhos + * + * Parts of this file are based on Ralink's 2.6.21 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + #include #include #include @@ -6,7 +19,10 @@ #include #include -#define RT2880_PCI_SLOT1_BASE 0x20000000 +#define RT2880_PCI_MEM_BASE 0x20000000 +#define RT2880_PCI_MEM_SIZE 0x10000000 +#define RT2880_PCI_IO_BASE 0x00460000 +#define RT2880_PCI_IO_SIZE 0x00010000 #define RT2880_PCI_REG_PCICFG_ADDR 0x00 #define RT2880_PCI_REG_PCIMSK_ADDR 0x0c @@ -24,7 +40,8 @@ #define PCI_ACCESS_READ 0 #define PCI_ACCESS_WRITE 1 -void __iomem *rt2880_pci_base; +static void __iomem *rt2880_pci_base; +static DEFINE_SPINLOCK(rt2880_pci_lock); static u32 rt2880_pci_reg_read(u32 reg) { @@ -36,8 +53,8 @@ static void rt2880_pci_reg_write(u32 val, u32 reg) writel(val, rt2880_pci_base + reg); } -static int config_access(unsigned char access_type, struct pci_bus *bus, - unsigned int devfn, unsigned char where, u32 *data) +static void config_access(unsigned char access_type, struct pci_bus *bus, + unsigned int devfn, unsigned char where, u32 *data) { unsigned int slot = PCI_SLOT(devfn); unsigned int address; @@ -51,24 +68,29 @@ static int config_access(unsigned char access_type, struct pci_bus *bus, rt2880_pci_reg_write(*data, RT2880_PCI_REG_CONFIG_DATA); else *data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA); - - return 0; } static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) { + unsigned long flags; u32 data = 0; - if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) - return PCIBIOS_DEVICE_NOT_FOUND; + spin_lock_irqsave(&rt2880_pci_lock, flags); + config_access(PCI_ACCESS_READ, bus, devfn, where, &data); + spin_unlock_irqrestore(&rt2880_pci_lock, flags); - if (size == 1) + switch (size) { + case 1: *val = (data >> ((where & 3) << 3)) & 0xff; - else if (size == 2) + break; + case 2: *val = (data >> ((where & 3) << 3)) & 0xffff; - else + break; + case 4: *val = data; + break; + } return PCIBIOS_SUCCESSFUL; } @@ -76,23 +98,29 @@ static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn, static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) { + unsigned long flags; u32 data = 0; - if (size == 4) { + spin_lock_irqsave(&rt2880_pci_lock, flags); + + switch (size) { + case 1: + config_access(PCI_ACCESS_READ, bus, devfn, where, &data); + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + break; + case 2: + config_access(PCI_ACCESS_READ, bus, devfn, where, &data); + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + break; + case 4: data = val; - } else { - if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) - return PCIBIOS_DEVICE_NOT_FOUND; - if (size == 1) - data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - else if (size == 2) - data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); + break; } - if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) - return PCIBIOS_DEVICE_NOT_FOUND; + config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data); + spin_unlock_irqrestore(&rt2880_pci_lock, flags); return PCIBIOS_SUCCESSFUL; } @@ -104,15 +132,15 @@ static struct pci_ops rt2880_pci_ops = { static struct resource rt2880_pci_io_resource = { .name = "PCI MEM space", - .start = 0x20000000, - .end = 0x2FFFFFFF, + .start = RT2880_PCI_MEM_BASE, + .end = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1, .flags = IORESOURCE_MEM, }; static struct resource rt2880_pci_mem_resource = { .name = "PCI IO space", - .start = 0x00460000, - .end = 0x0046FFFF, + .start = RT2880_PCI_IO_BASE, + .end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1, .flags = IORESOURCE_IO, }; @@ -122,28 +150,36 @@ static struct pci_controller rt2880_pci_controller = { .io_resource = &rt2880_pci_mem_resource, }; -void inline read_config(unsigned long bus, unsigned long dev, - unsigned long func, unsigned long reg, - unsigned long *val) +static inline void read_config(unsigned long bus, unsigned long dev, + unsigned long func, unsigned long reg, + unsigned long *val) { unsigned long address; + unsigned long flags; address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000; + + spin_lock_irqsave(&rt2880_pci_lock, flags); rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); *val = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA); + spin_unlock_irqrestore(&rt2880_pci_lock, flags); } -void inline write_config(unsigned long bus, unsigned long dev, - unsigned long func, unsigned long reg, - unsigned long val) +static inline void write_config(unsigned long bus, unsigned long dev, + unsigned long func, unsigned long reg, + unsigned long val) { unsigned long address; + unsigned long flags; address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000; + + spin_lock_irqsave(&rt2880_pci_lock, flags); rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA); + spin_unlock_irqrestore(&rt2880_pci_lock, flags); } int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) @@ -194,8 +230,8 @@ static int __init rt2880_pci_init(void) rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL); rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR); - rt2880_pci_reg_write(RT2880_PCI_SLOT1_BASE, RT2880_PCI_REG_MEMBASE); - rt2880_pci_reg_write(0x00460000, RT2880_PCI_REG_IOBASE); + rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE); + rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE); rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR); rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID); rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);