X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/297e15bc7053d87ae683c9bdbdb8da16e09c7c1b..ae774d3615d6a2c66871accfd3b07ca8459ef7c7:/target/linux/generic/patches-2.6.30/941-ssb_update.patch diff --git a/target/linux/generic/patches-2.6.30/941-ssb_update.patch b/target/linux/generic/patches-2.6.30/941-ssb_update.patch index 3b54067d7..b27270aba 100644 --- a/target/linux/generic/patches-2.6.30/941-ssb_update.patch +++ b/target/linux/generic/patches-2.6.30/941-ssb_update.patch @@ -33,7 +33,22 @@ ssb-y += driver_chipcommon.o --- a/drivers/ssb/b43_pci_bridge.c +++ b/drivers/ssb/b43_pci_bridge.c -@@ -24,6 +24,7 @@ static const struct pci_device_id b43_pc +@@ -5,12 +5,13 @@ + * because of its small size we include it in the SSB core + * instead of creating a standalone module. + * +- * Copyright 2007 Michael Buesch ++ * Copyright 2007 Michael Buesch + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + + #include ++#include + #include + + #include "ssb_private.h" +@@ -24,6 +25,7 @@ static const struct pci_device_id b43_pc { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4312) }, { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4315) }, { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4318) }, @@ -43,6 +58,15 @@ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) }, --- a/drivers/ssb/driver_chipcommon.c +++ b/drivers/ssb/driver_chipcommon.c +@@ -3,7 +3,7 @@ + * Broadcom ChipCommon core driver + * + * Copyright 2005, Broadcom Corporation +- * Copyright 2006, 2007, Michael Buesch ++ * Copyright 2006, 2007, Michael Buesch + * + * Licensed under the GNU/GPL. See COPYING for details. + */ @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb if (!ccdev) return; @@ -192,7 +216,16 @@ { --- a/drivers/ssb/driver_chipcommon_pmu.c +++ b/drivers/ssb/driver_chipcommon_pmu.c -@@ -28,6 +28,21 @@ static void ssb_chipco_pll_write(struct +@@ -2,7 +2,7 @@ + * Sonics Silicon Backplane + * Broadcom ChipCommon Power Management Unit driver + * +- * Copyright 2009, Michael Buesch ++ * Copyright 2009, Michael Buesch + * Copyright 2007, Broadcom Corporation + * + * Licensed under the GNU/GPL. See COPYING for details. +@@ -28,6 +28,21 @@ static void ssb_chipco_pll_write(struct chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, value); } @@ -256,7 +289,7 @@ u32 pmucap; if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU)) -@@ -494,15 +518,91 @@ void ssb_pmu_init(struct ssb_chipcommon +@@ -494,15 +518,91 @@ void ssb_pmu_init(struct ssb_chipcommon ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev, pmucap); @@ -359,6 +392,15 @@ +EXPORT_SYMBOL(ssb_pmu_set_ldo_paref); --- a/drivers/ssb/driver_gige.c +++ b/drivers/ssb/driver_gige.c +@@ -3,7 +3,7 @@ + * Broadcom Gigabit Ethernet core driver + * + * Copyright 2008, Broadcom Corporation +- * Copyright 2008, Michael Buesch ++ * Copyright 2008, Michael Buesch + * + * Licensed under the GNU/GPL. See COPYING for details. + */ @@ -12,6 +12,7 @@ #include #include @@ -403,6 +445,15 @@ u32 base, tmslow, tmshigh; --- a/drivers/ssb/driver_mipscore.c +++ b/drivers/ssb/driver_mipscore.c +@@ -3,7 +3,7 @@ + * Broadcom MIPS core driver + * + * Copyright 2005, Broadcom Corporation +- * Copyright 2006, 2007, Michael Buesch ++ * Copyright 2006, 2007, Michael Buesch + * + * Licensed under the GNU/GPL. See COPYING for details. + */ @@ -49,29 +49,54 @@ static const u32 ipsflag_irq_shift[] = { static inline u32 ssb_irqflag(struct ssb_device *dev) @@ -567,6 +618,15 @@ ssb_mips_flash_detect(mcore); --- a/drivers/ssb/driver_pcicore.c +++ b/drivers/ssb/driver_pcicore.c +@@ -3,7 +3,7 @@ + * Broadcom PCI-core driver + * + * Copyright 2005, Broadcom Corporation +- * Copyright 2006, 2007, Michael Buesch ++ * Copyright 2006, 2007, Michael Buesch + * + * Licensed under the GNU/GPL. See COPYING for details. + */ @@ -15,6 +15,11 @@ #include "ssb_private.h" @@ -646,7 +706,7 @@ { struct ssb_bus *bus = pc->dev->bus; u16 chipid_top; -@@ -432,25 +408,133 @@ static int pcicore_is_in_hostmode(struct +@@ -432,25 +408,137 @@ static int pcicore_is_in_hostmode(struct } #endif /* CONFIG_SSB_PCICORE_HOSTMODE */ @@ -759,10 +819,15 @@ -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc) +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc) { -+ ssb_pcicore_fix_sprom_core_index(pc); ++ struct ssb_device *pdev = pc->dev; ++ struct ssb_bus *bus = pdev->bus; ++ ++ if (bus->bustype == SSB_BUSTYPE_PCI) ++ ssb_pcicore_fix_sprom_core_index(pc); + /* Disable PCI interrupts. */ - ssb_write32(pc->dev, SSB_INTVEC, 0); +- ssb_write32(pc->dev, SSB_INTVEC, 0); ++ ssb_write32(pdev, SSB_INTVEC, 0); + + /* Additional PCIe always once-executed workarounds */ + if (pc->dev->id.coreid == SSB_DEV_PCIE) { @@ -784,7 +849,7 @@ if (!ssb_device_is_enabled(dev)) ssb_device_enable(dev, 0); -@@ -475,58 +559,104 @@ static void ssb_pcie_write(struct ssb_pc +@@ -475,58 +563,104 @@ static void ssb_pcie_write(struct ssb_pc pcicore_write32(pc, 0x134, data); } @@ -914,7 +979,7 @@ } int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc, -@@ -551,13 +681,13 @@ int ssb_pcicore_dev_irqvecs_enable(struc +@@ -551,13 +685,13 @@ int ssb_pcicore_dev_irqvecs_enable(struc might_sleep_if(pdev->id.coreid != SSB_DEV_PCI); /* Enable interrupts for this device. */ @@ -930,7 +995,7 @@ err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp); if (err) goto out; -@@ -579,48 +709,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc +@@ -579,48 +713,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc if (pc->setup_done) goto out; if (pdev->id.coreid == SSB_DEV_PCI) { @@ -983,7 +1048,22 @@ out: --- a/drivers/ssb/main.c +++ b/drivers/ssb/main.c -@@ -17,6 +17,8 @@ +@@ -3,7 +3,7 @@ + * Subsystem core + * + * Copyright 2005, Broadcom Corporation +- * Copyright 2006, 2007, Michael Buesch ++ * Copyright 2006, 2007, Michael Buesch + * + * Licensed under the GNU/GPL. See COPYING for details. + */ +@@ -12,11 +12,14 @@ + + #include + #include ++#include + #include + #include #include #include #include @@ -992,7 +1072,7 @@ #include #include -@@ -88,6 +90,25 @@ found: +@@ -88,6 +91,25 @@ found: } #endif /* CONFIG_SSB_PCMCIAHOST */ @@ -1018,7 +1098,7 @@ int ssb_for_each_bus_call(unsigned long data, int (*func)(struct ssb_bus *bus, unsigned long data)) { -@@ -120,6 +141,19 @@ static void ssb_device_put(struct ssb_de +@@ -120,6 +142,19 @@ static void ssb_device_put(struct ssb_de put_device(dev->dev); } @@ -1038,7 +1118,7 @@ static int ssb_device_resume(struct device *dev) { struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); -@@ -190,90 +224,81 @@ int ssb_bus_suspend(struct ssb_bus *bus) +@@ -190,90 +225,81 @@ int ssb_bus_suspend(struct ssb_bus *bus) EXPORT_SYMBOL(ssb_bus_suspend); #ifdef CONFIG_SSB_SPROM @@ -1181,7 +1261,7 @@ } #endif /* CONFIG_SSB_SPROM */ -@@ -360,6 +385,35 @@ static int ssb_device_uevent(struct devi +@@ -360,6 +386,35 @@ static int ssb_device_uevent(struct devi ssb_dev->id.revision); } @@ -1217,7 +1297,7 @@ static struct bus_type ssb_bustype = { .name = "ssb", .match = ssb_bus_match, -@@ -369,6 +423,7 @@ static struct bus_type ssb_bustype = { +@@ -369,6 +424,7 @@ static struct bus_type ssb_bustype = { .suspend = ssb_device_suspend, .resume = ssb_device_resume, .uevent = ssb_device_uevent, @@ -1225,7 +1305,7 @@ }; static void ssb_buses_lock(void) -@@ -461,6 +516,7 @@ static int ssb_devices_register(struct s +@@ -461,6 +517,7 @@ static int ssb_devices_register(struct s #ifdef CONFIG_SSB_PCIHOST sdev->irq = bus->host_pci->irq; dev->parent = &bus->host_pci->dev; @@ -1233,7 +1313,7 @@ #endif break; case SSB_BUSTYPE_PCMCIA: -@@ -469,8 +525,14 @@ static int ssb_devices_register(struct s +@@ -469,8 +526,14 @@ static int ssb_devices_register(struct s dev->parent = &bus->host_pcmcia->dev; #endif break; @@ -1248,7 +1328,7 @@ break; } -@@ -497,7 +559,7 @@ error: +@@ -497,7 +560,7 @@ error: } /* Needs ssb_buses_lock() */ @@ -1257,7 +1337,7 @@ { struct ssb_bus *bus, *n; int err = 0; -@@ -708,9 +770,9 @@ out: +@@ -708,9 +771,9 @@ out: return err; } @@ -1270,7 +1350,7 @@ { int err; -@@ -724,12 +786,18 @@ static int ssb_bus_register(struct ssb_b +@@ -724,12 +787,18 @@ static int ssb_bus_register(struct ssb_b err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); if (err) goto out; @@ -1290,7 +1370,7 @@ /* Init PCI-host device (if any) */ err = ssb_pci_init(bus); -@@ -776,6 +844,8 @@ err_pci_exit: +@@ -776,6 +845,8 @@ err_pci_exit: ssb_pci_exit(bus); err_unmap: ssb_iounmap(bus); @@ -1299,7 +1379,7 @@ err_disable_xtal: ssb_buses_unlock(); ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); -@@ -783,8 +853,8 @@ err_disable_xtal: +@@ -783,8 +854,8 @@ err_disable_xtal: } #ifdef CONFIG_SSB_PCIHOST @@ -1310,7 +1390,7 @@ { int err; -@@ -796,6 +866,9 @@ int ssb_bus_pcibus_register(struct ssb_b +@@ -796,6 +867,9 @@ int ssb_bus_pcibus_register(struct ssb_b if (!err) { ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on " "PCI device %s\n", dev_name(&host_pci->dev)); @@ -1320,7 +1400,7 @@ } return err; -@@ -804,9 +877,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register); +@@ -804,9 +878,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register); #endif /* CONFIG_SSB_PCIHOST */ #ifdef CONFIG_SSB_PCMCIAHOST @@ -1333,7 +1413,7 @@ { int err; -@@ -825,9 +898,32 @@ int ssb_bus_pcmciabus_register(struct ss +@@ -825,9 +899,32 @@ int ssb_bus_pcmciabus_register(struct ss EXPORT_SYMBOL(ssb_bus_pcmciabus_register); #endif /* CONFIG_SSB_PCMCIAHOST */ @@ -1369,7 +1449,7 @@ { int err; -@@ -908,8 +1004,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32 +@@ -908,8 +1005,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32 switch (plltype) { case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ if (m & SSB_CHIPCO_CLK_T6_MMASK) @@ -1380,7 +1460,7 @@ case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ -@@ -1024,23 +1120,22 @@ static u32 ssb_tmslow_reject_bitmask(str +@@ -1024,23 +1121,22 @@ static u32 ssb_tmslow_reject_bitmask(str { u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV; @@ -1411,7 +1491,7 @@ } int ssb_device_is_enabled(struct ssb_device *dev) -@@ -1099,10 +1194,10 @@ void ssb_device_enable(struct ssb_device +@@ -1099,10 +1195,10 @@ void ssb_device_enable(struct ssb_device } EXPORT_SYMBOL(ssb_device_enable); @@ -1425,7 +1505,7 @@ { int i; u32 val; -@@ -1110,7 +1205,7 @@ static int ssb_wait_bit(struct ssb_devic +@@ -1110,7 +1206,7 @@ static int ssb_wait_bit(struct ssb_devic for (i = 0; i < timeout; i++) { val = ssb_read32(dev, reg); if (set) { @@ -1434,7 +1514,7 @@ return 0; } else { if (!(val & bitmask)) -@@ -1127,20 +1222,38 @@ static int ssb_wait_bit(struct ssb_devic +@@ -1127,20 +1223,38 @@ static int ssb_wait_bit(struct ssb_devic void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags) { @@ -1482,19 +1562,43 @@ ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_RESET | -@@ -1155,7 +1268,10 @@ u32 ssb_dma_translation(struct ssb_devic +@@ -1149,13 +1263,34 @@ void ssb_device_disable(struct ssb_devic + } + EXPORT_SYMBOL(ssb_device_disable); + ++/* Some chipsets need routing known for PCIe and 64-bit DMA */ ++static bool ssb_dma_translation_special_bit(struct ssb_device *dev) ++{ ++ u16 chip_id = dev->bus->chip_id; ++ ++ if (dev->id.coreid == SSB_DEV_80211) { ++ return (chip_id == 0x4322 || chip_id == 43221 || ++ chip_id == 43231 || chip_id == 43222); ++ } ++ ++ return 0; ++} ++ + u32 ssb_dma_translation(struct ssb_device *dev) + { + switch (dev->bus->bustype) { case SSB_BUSTYPE_SSB: return 0; case SSB_BUSTYPE_PCI: - return SSB_PCI_DMA; -+ if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) ++ if (dev->bus->host_pci->is_pcie && ++ ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) { + return SSB_PCIE_DMA_H32; -+ else -+ return SSB_PCI_DMA; ++ } else { ++ if (ssb_dma_translation_special_bit(dev)) ++ return SSB_PCIE_DMA_H32; ++ else ++ return SSB_PCI_DMA; ++ } default: __ssb_dma_not_implemented(dev); } -@@ -1272,20 +1388,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown); +@@ -1272,20 +1407,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown); int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl) { @@ -1519,7 +1623,7 @@ return 0; error: ssb_printk(KERN_ERR PFX "Bus powerup failed\n"); -@@ -1293,6 +1409,37 @@ error: +@@ -1293,6 +1428,37 @@ error: } EXPORT_SYMBOL(ssb_bus_powerup); @@ -1557,7 +1661,7 @@ u32 ssb_admatch_base(u32 adm) { u32 base = 0; -@@ -1358,8 +1505,10 @@ static int __init ssb_modinit(void) +@@ -1358,8 +1524,10 @@ static int __init ssb_modinit(void) ssb_buses_lock(); err = ssb_attach_queued_buses(); ssb_buses_unlock(); @@ -1569,7 +1673,7 @@ err = b43_pci_ssb_bridge_init(); if (err) { -@@ -1375,7 +1524,7 @@ static int __init ssb_modinit(void) +@@ -1375,7 +1543,7 @@ static int __init ssb_modinit(void) /* don't fail SSB init because of this */ err = 0; } @@ -1580,6 +1684,15 @@ /* ssb must be initialized after PCI but before the ssb drivers. --- a/drivers/ssb/pci.c +++ b/drivers/ssb/pci.c +@@ -1,7 +1,7 @@ + /* + * Sonics Silicon Backplane PCI-Hostbus related functions. + * +- * Copyright (C) 2005-2006 Michael Buesch ++ * Copyright (C) 2005-2006 Michael Buesch + * Copyright (C) 2005 Martin Langer + * Copyright (C) 2005 Stefano Brivio + * Copyright (C) 2005 Danny van Dyk @@ -17,6 +17,7 @@ #include @@ -1607,7 +1720,7 @@ static inline u8 ssb_crc8(u8 crc, u8 data) { -@@ -247,7 +254,7 @@ static int sprom_do_read(struct ssb_bus +@@ -247,7 +254,7 @@ static int sprom_do_read(struct ssb_bus int i; for (i = 0; i < bus->sprom_size; i++) @@ -1687,7 +1800,7 @@ } SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A, SSB_SPROM4_ANTAVAIL_A_SHIFT); -@@ -464,6 +515,8 @@ static void sprom_extract_r45(struct ssb +@@ -464,22 +515,32 @@ static void sprom_extract_r45(struct ssb memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24, sizeof(out->antenna_gain.ghz5)); @@ -1696,7 +1809,17 @@ /* TODO - get remaining rev 4 stuff needed */ } -@@ -474,12 +527,14 @@ static void sprom_extract_r8(struct ssb_ + static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in) + { + int i; +- u16 v; ++ u16 v, o; ++ u16 pwr_info_offset[] = { ++ SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1, ++ SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3 ++ }; ++ BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) != ++ ARRAY_SIZE(out->core_pwr_info)); /* extract the MAC address */ for (i = 0; i < 3; i++) { @@ -1712,7 +1835,7 @@ SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A, SSB_SPROM8_ANTAVAIL_A_SHIFT); SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG, -@@ -490,12 +545,55 @@ static void sprom_extract_r8(struct ssb_ +@@ -490,12 +551,55 @@ static void sprom_extract_r8(struct ssb_ SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0); SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A, SSB_SPROM8_ITSSI_A_SHIFT); @@ -1768,16 +1891,71 @@ /* Extract the antenna gain values. */ SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01, -@@ -509,6 +607,8 @@ static void sprom_extract_r8(struct ssb_ +@@ -509,6 +613,63 @@ static void sprom_extract_r8(struct ssb_ memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24, sizeof(out->antenna_gain.ghz5)); ++ /* Extract cores power info info */ ++ for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) { ++ o = pwr_info_offset[i]; ++ SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI, ++ SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT); ++ SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI, ++ SSB_SPROM8_2G_MAXP, 0); ++ ++ SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0); ++ SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0); ++ SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0); ++ ++ SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI, ++ SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT); ++ SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI, ++ SSB_SPROM8_5G_MAXP, 0); ++ SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP, ++ SSB_SPROM8_5GH_MAXP, 0); ++ SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP, ++ SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT); ++ ++ SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0); ++ } ++ ++ /* Extract FEM info */ ++ SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT); ++ SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT); ++ SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT); ++ SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT); ++ SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT); ++ ++ SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT); ++ SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT); ++ SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT); ++ SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT); ++ SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT); ++ + sprom_extract_r458(out, in); + /* TODO - get remaining rev 8 stuff needed */ } -@@ -521,36 +621,34 @@ static int sprom_extract(struct ssb_bus +@@ -521,36 +682,34 @@ static int sprom_extract(struct ssb_bus ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision); memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */ memset(out->et1mac, 0xFF, 6); @@ -1835,7 +2013,7 @@ } if (out->boardflags_lo == 0xFFFF) -@@ -564,13 +662,34 @@ static int sprom_extract(struct ssb_bus +@@ -564,13 +723,34 @@ static int sprom_extract(struct ssb_bus static int ssb_pci_sprom_get(struct ssb_bus *bus, struct ssb_sprom *sprom) { @@ -1873,7 +2051,7 @@ bus->sprom_size = SSB_SPROMSIZE_WORDS_R123; sprom_do_read(bus, buf); err = sprom_check_crc(buf, bus->sprom_size); -@@ -580,17 +699,24 @@ static int ssb_pci_sprom_get(struct ssb_ +@@ -580,17 +760,24 @@ static int ssb_pci_sprom_get(struct ssb_ buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16), GFP_KERNEL); if (!buf) @@ -1903,7 +2081,7 @@ err = 0; goto out_free; } -@@ -602,19 +728,15 @@ static int ssb_pci_sprom_get(struct ssb_ +@@ -602,19 +789,15 @@ static int ssb_pci_sprom_get(struct ssb_ out_free: kfree(buf); @@ -1928,7 +2106,14 @@ int ssb_pci_get_invariants(struct ssb_bus *bus, --- a/drivers/ssb/pcihost_wrapper.c +++ b/drivers/ssb/pcihost_wrapper.c -@@ -12,6 +12,7 @@ +@@ -6,12 +6,13 @@ + * Copyright (c) 2005 Stefano Brivio + * Copyright (c) 2005 Danny van Dyk + * Copyright (c) 2005 Andreas Jaggi +- * Copyright (c) 2005-2007 Michael Buesch ++ * Copyright (c) 2005-2007 Michael Buesch + * + * Licensed under the GNU/GPL. See COPYING for details. */ #include @@ -1976,6 +2161,15 @@ driver->remove = ssb_pcihost_remove; --- a/drivers/ssb/pcmcia.c +++ b/drivers/ssb/pcmcia.c +@@ -3,7 +3,7 @@ + * PCMCIA-Hostbus related functions + * + * Copyright 2006 Johannes Berg +- * Copyright 2007-2008 Michael Buesch ++ * Copyright 2007-2008 Michael Buesch + * + * Licensed under the GNU/GPL. See COPYING for details. + */ @@ -583,7 +583,7 @@ static int ssb_pcmcia_sprom_write_all(st ssb_printk("."); err = ssb_pcmcia_sprom_write(bus, i, sprom[i]); @@ -2003,10 +2197,7 @@ +static int ssb_pcmcia_get_mac(struct pcmcia_device *p_dev, + tuple_t *tuple, + void *priv) - { -- tuple_t tuple; -- int res; -- unsigned char buf[32]; ++{ + struct ssb_sprom *sprom = priv; + + if (tuple->TupleData[0] != CISTPL_FUNCE_LAN_NODE_ID) @@ -2022,7 +2213,10 @@ +static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev, + tuple_t *tuple, + void *priv) -+{ + { +- tuple_t tuple; +- int res; +- unsigned char buf[32]; + struct ssb_init_invariants *iv = priv; struct ssb_sprom *sprom = &iv->sprom; struct ssb_boardinfo *bi = &iv->boardinfo; @@ -2249,6 +2443,15 @@ --- a/drivers/ssb/scan.c +++ b/drivers/ssb/scan.c +@@ -2,7 +2,7 @@ + * Sonics Silicon Backplane + * Bus scanning + * +- * Copyright (C) 2005-2007 Michael Buesch ++ * Copyright (C) 2005-2007 Michael Buesch + * Copyright (C) 2005 Martin Langer + * Copyright (C) 2005 Stefano Brivio + * Copyright (C) 2005 Danny van Dyk @@ -162,6 +162,8 @@ static u8 chipid_to_nrcores(u16 chipid) static u32 scan_read32(struct ssb_bus *bus, u8 current_coreidx, u16 offset) @@ -2290,7 +2493,7 @@ } bus->mmio = NULL; bus->mapped_device = NULL; -@@ -230,6 +241,10 @@ static void __iomem *ssb_ioremap(struct +@@ -230,6 +241,10 @@ static void __iomem *ssb_ioremap(struct SSB_BUG_ON(1); /* Can't reach this code. */ #endif break; @@ -2360,7 +2563,7 @@ + * + * Based on drivers/ssb/pcmcia.c + * Copyright 2006 Johannes Berg -+ * Copyright 2007-2008 Michael Buesch ++ * Copyright 2007-2008 Michael Buesch + * + * Licensed under the GNU/GPL. See COPYING for details. + * @@ -2964,6 +3167,15 @@ +} --- a/drivers/ssb/sprom.c +++ b/drivers/ssb/sprom.c +@@ -2,7 +2,7 @@ + * Sonics Silicon Backplane + * Common SPROM support routines + * +- * Copyright (C) 2005-2008 Michael Buesch ++ * Copyright (C) 2005-2008 Michael Buesch + * Copyright (C) 2005 Martin Langer + * Copyright (C) 2005 Stefano Brivio + * Copyright (C) 2005 Danny van Dyk @@ -13,8 +13,11 @@ #include "ssb_private.h" @@ -3043,29 +3255,31 @@ /** - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found. -+ * ssb_arch_register_fallback_sprom - Registers a method providing a -+ * fallback SPROM if no SPROM is found. - * +- * - * @sprom: The SPROM data structure to register. -+ * @sprom_callback: The callback function. - * +- * - * With this function the architecture implementation may register a fallback - * SPROM data structure. The fallback is only used for PCI based SSB devices, - * where no valid SPROM can be found in the shadow registers. -+ * With this function the architecture implementation may register a -+ * callback handler which fills the SPROM data structure. The fallback is -+ * only used for PCI based SSB devices, where no valid SPROM can be found -+ * in the shadow registers. ++ * ssb_arch_register_fallback_sprom - Registers a method providing a ++ * fallback SPROM if no SPROM is found. * - * This function is useful for weird architectures that have a half-assed SSB device - * hardwired to their PCI bus. -+ * This function is useful for weird architectures that have a half-assed -+ * SSB device hardwired to their PCI bus. ++ * @sprom_callback: The callback function. * - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently - * don't use this fallback. - * Architectures must provide the SPROM for native SSB devices anyway, - * so the fallback also isn't used for native devices. ++ * With this function the architecture implementation may register a ++ * callback handler which fills the SPROM data structure. The fallback is ++ * only used for PCI based SSB devices, where no valid SPROM can be found ++ * in the shadow registers. ++ * ++ * This function is useful for weird architectures that have a half-assed ++ * SSB device hardwired to their PCI bus. ++ * + * Note that it does only work with PCI attached SSB devices. PCMCIA + * devices currently don't use this fallback. + * Architectures must provide the SPROM for native SSB devices anyway, so @@ -3219,9 +3433,25 @@ #define PCI_DEVICE_ID_TIGON3_5752M 0x1601 --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h -@@ -27,24 +27,60 @@ struct ssb_sprom { +@@ -16,6 +16,12 @@ struct pcmcia_device; + struct ssb_bus; + struct ssb_driver; + ++struct ssb_sprom_core_pwr_info { ++ u8 itssi_2g, itssi_5g; ++ u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh; ++ u16 pa_2g[3], pa_5gl[3], pa_5g[3], pa_5gh[3]; ++}; ++ + struct ssb_sprom { + u8 revision; + u8 il0mac[6]; /* MAC address for 802.11b/g */ +@@ -25,26 +31,64 @@ struct ssb_sprom { + u8 et1phyaddr; /* MII address for enet1 */ + u8 et0mdcport; /* MDIO for enet0 */ u8 et1mdcport; /* MDIO for enet1 */ - u8 board_rev; /* Board revision number from SPROM. */ +- u8 board_rev; /* Board revision number from SPROM. */ ++ u16 board_rev; /* Board revision number from SPROM. */ u8 country_code; /* Country Code */ - u8 ant_available_a; /* A-PHY antenna available bits (up to 4) */ - u8 ant_available_bg; /* B/G-PHY antenna available bits (up to 4) */ @@ -3283,14 +3513,25 @@ + u16 boardflags2_lo; /* Board flags (bits 32-47) */ + u16 boardflags2_hi; /* Board flags (bits 48-63) */ + /* TODO store board flags in a single u64 */ ++ ++ struct ssb_sprom_core_pwr_info core_pwr_info[4]; /* Antenna gain values for up to 4 antennas * on each band. Values in dBm/4 (Q5.2). Negative gain means the -@@ -58,14 +94,14 @@ struct ssb_sprom { +@@ -58,14 +102,23 @@ struct ssb_sprom { } ghz5; /* 5GHz band */ } antenna_gain; - /* TODO - add any parameters needed from rev 2, 3, or 4 SPROMs */ ++ struct { ++ struct { ++ u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut; ++ } ghz2; ++ struct { ++ u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut; ++ } ghz5; ++ } fem; ++ + /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */ }; @@ -3303,7 +3544,7 @@ }; -@@ -137,7 +173,7 @@ struct ssb_device { +@@ -137,7 +190,7 @@ struct ssb_device { * is an optimization. */ const struct ssb_bus_ops *ops; @@ -3312,7 +3553,21 @@ struct ssb_bus *bus; struct ssb_device_id id; -@@ -208,6 +244,7 @@ enum ssb_bustype { +@@ -195,10 +248,9 @@ struct ssb_driver { + #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv) + + extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner); +-static inline int ssb_driver_register(struct ssb_driver *drv) +-{ +- return __ssb_driver_register(drv, THIS_MODULE); +-} ++#define ssb_driver_register(drv) \ ++ __ssb_driver_register(drv, THIS_MODULE) ++ + extern void ssb_driver_unregister(struct ssb_driver *drv); + + +@@ -208,6 +260,7 @@ enum ssb_bustype { SSB_BUSTYPE_SSB, /* This SSB bus is the system bus */ SSB_BUSTYPE_PCI, /* SSB is connected to PCI bus */ SSB_BUSTYPE_PCMCIA, /* SSB is connected to PCMCIA bus */ @@ -3320,7 +3575,7 @@ }; /* board_vendor */ -@@ -238,20 +275,33 @@ struct ssb_bus { +@@ -238,20 +291,33 @@ struct ssb_bus { const struct ssb_bus_ops *ops; @@ -3362,7 +3617,7 @@ #ifdef CONFIG_SSB_SPROM /* Mutex to protect the SPROM writing. */ -@@ -260,7 +310,8 @@ struct ssb_bus { +@@ -260,7 +326,8 @@ struct ssb_bus { /* ID information about the Chip. */ u16 chip_id; @@ -3372,7 +3627,7 @@ u16 sprom_size; /* number of words in sprom */ u8 chip_package; -@@ -306,6 +357,11 @@ struct ssb_bus { +@@ -306,6 +373,11 @@ struct ssb_bus { #endif /* DEBUG */ }; @@ -3384,7 +3639,7 @@ /* The initialization-invariants. */ struct ssb_init_invariants { /* Versioning information about the PCB. */ -@@ -336,12 +392,23 @@ extern int ssb_bus_pcmciabus_register(st +@@ -336,12 +408,23 @@ extern int ssb_bus_pcmciabus_register(st struct pcmcia_device *pcmcia_dev, unsigned long baseaddr); #endif /* CONFIG_SSB_PCMCIAHOST */ @@ -3409,7 +3664,7 @@ /* Suspend a SSB bus. * Call this from the parent bus suspend routine. */ -@@ -612,6 +679,7 @@ extern int ssb_bus_may_powerdown(struct +@@ -612,6 +695,7 @@ extern int ssb_bus_may_powerdown(struct * Otherwise static always-on powercontrol will be used. */ extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl); @@ -3419,6 +3674,15 @@ extern u32 ssb_admatch_base(u32 adm); --- a/include/linux/ssb/ssb_driver_chipcommon.h +++ b/include/linux/ssb/ssb_driver_chipcommon.h +@@ -8,7 +8,7 @@ + * gpio interface, extbus, and support for serial and parallel flashes. + * + * Copyright 2005, Broadcom Corporation +- * Copyright 2006, Michael Buesch ++ * Copyright 2006, Michael Buesch + * + * Licensed under the GPL version 2. See COPYING for details. + */ @@ -53,6 +53,7 @@ #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */ #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */ @@ -3669,7 +3933,7 @@ #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */ #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */ #define SSB_SPROM3_CCKPO_2M_SHIFT 4 -@@ -264,104 +267,200 @@ +@@ -264,104 +267,291 @@ #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */ /* SPROM Revision 4 */ @@ -3893,6 +4157,56 @@ +#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */ +#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */ +#define SSB_SPROM8_RXPO5G_SHIFT 8 ++#define SSB_SPROM8_FEM2G 0x00AE ++#define SSB_SPROM8_FEM5G 0x00B0 ++#define SSB_SROM8_FEM_TSSIPOS 0x0001 ++#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0 ++#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006 ++#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1 ++#define SSB_SROM8_FEM_PDET_RANGE 0x00F8 ++#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3 ++#define SSB_SROM8_FEM_TR_ISO 0x0700 ++#define SSB_SROM8_FEM_TR_ISO_SHIFT 8 ++#define SSB_SROM8_FEM_ANTSWLUT 0xF800 ++#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11 ++#define SSB_SPROM8_THERMAL 0x00B2 ++#define SSB_SPROM8_MPWR_RAWTS 0x00B4 ++#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6 ++#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8 ++#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA ++ ++/* There are 4 blocks with power info sharing the same layout */ ++#define SSB_SROM8_PWR_INFO_CORE0 0x00C0 ++#define SSB_SROM8_PWR_INFO_CORE1 0x00E0 ++#define SSB_SROM8_PWR_INFO_CORE2 0x0100 ++#define SSB_SROM8_PWR_INFO_CORE3 0x0120 ++ ++#define SSB_SROM8_2G_MAXP_ITSSI 0x00 ++#define SSB_SPROM8_2G_MAXP 0x00FF ++#define SSB_SPROM8_2G_ITSSI 0xFF00 ++#define SSB_SPROM8_2G_ITSSI_SHIFT 8 ++#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */ ++#define SSB_SROM8_2G_PA_1 0x04 ++#define SSB_SROM8_2G_PA_2 0x06 ++#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */ ++#define SSB_SPROM8_5G_MAXP 0x00FF ++#define SSB_SPROM8_5G_ITSSI 0xFF00 ++#define SSB_SPROM8_5G_ITSSI_SHIFT 8 ++#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */ ++#define SSB_SPROM8_5GH_MAXP 0x00FF ++#define SSB_SPROM8_5GL_MAXP 0xFF00 ++#define SSB_SPROM8_5GL_MAXP_SHIFT 8 ++#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */ ++#define SSB_SROM8_5G_PA_1 0x0E ++#define SSB_SROM8_5G_PA_2 0x10 ++#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */ ++#define SSB_SROM8_5GL_PA_1 0x14 ++#define SSB_SROM8_5GL_PA_2 0x16 ++#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */ ++#define SSB_SROM8_5GH_PA_1 0x1A ++#define SSB_SROM8_5GH_PA_2 0x1C ++ ++/* TODO: Make it deprecated */ +#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */ +#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */ #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ @@ -3919,11 +4233,74 @@ +#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */ +#define SSB_SPROM8_PA1HIB1 0x00DA +#define SSB_SPROM8_PA1HIB2 0x00DC ++ +#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */ +#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */ +#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */ +#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */ +#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */ ++ ++/* Values for boardflags_lo read from SPROM */ ++#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */ ++#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */ ++#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */ ++#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */ ++#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */ ++#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */ ++#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */ ++#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */ ++#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */ ++#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */ ++#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */ ++#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */ ++#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */ ++#define SSB_BFL_HGPA 0x2000 /* had high gain PA */ ++#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */ ++#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */ ++ ++/* Values for boardflags_hi read from SPROM */ ++#define SSB_BFH_NOPA 0x0001 /* has no PA */ ++#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */ ++#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */ ++#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */ ++#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */ ++#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */ ++#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */ ++ ++/* Values for boardflags2_lo read from SPROM */ ++#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */ ++#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */ ++#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */ ++#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */ ++#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */ ++#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */ ++#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */ ++#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */ ++#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */ ++#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */ ++#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */ /* Values for SSB_SPROM1_BINF_CCODE */ enum { +--- a/drivers/ssb/driver_extif.c ++++ b/drivers/ssb/driver_extif.c +@@ -3,7 +3,7 @@ + * Broadcom EXTIF core driver + * + * Copyright 2005, Broadcom Corporation +- * Copyright 2006, 2007, Michael Buesch ++ * Copyright 2006, 2007, Michael Buesch + * Copyright 2006, 2007, Felix Fietkau + * Copyright 2007, Aurelien Jarno + * +--- a/drivers/ssb/embedded.c ++++ b/drivers/ssb/embedded.c +@@ -3,7 +3,7 @@ + * Embedded systems support code + * + * Copyright 2005-2008, Broadcom Corporation +- * Copyright 2006-2008, Michael Buesch ++ * Copyright 2006-2008, Michael Buesch + * + * Licensed under the GNU/GPL. See COPYING for details. + */