X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/2e7da1b948f9bf1946f992e7bafe27b913798367..19b6acd0905aef3f8718e694c0264ef5ddcf6403:/target/linux/brcm47xx/patches-2.6.32/220-bcm5354.patch?ds=sidebyside diff --git a/target/linux/brcm47xx/patches-2.6.32/220-bcm5354.patch b/target/linux/brcm47xx/patches-2.6.32/220-bcm5354.patch index 6aedfb2e5..1d75e171d 100644 --- a/target/linux/brcm47xx/patches-2.6.32/220-bcm5354.patch +++ b/target/linux/brcm47xx/patches-2.6.32/220-bcm5354.patch @@ -1,6 +1,6 @@ --- a/drivers/ssb/driver_chipcommon.c +++ b/drivers/ssb/driver_chipcommon.c -@@ -258,6 +258,8 @@ void ssb_chipco_resume(struct ssb_chipco +@@ -260,6 +260,8 @@ void ssb_chipco_resume(struct ssb_chipco void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc, u32 *plltype, u32 *n, u32 *m) { @@ -9,7 +9,7 @@ *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N); *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); switch (*plltype) { -@@ -281,6 +283,8 @@ void ssb_chipco_get_clockcpu(struct ssb_ +@@ -283,6 +285,8 @@ void ssb_chipco_get_clockcpu(struct ssb_ void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc, u32 *plltype, u32 *n, u32 *m) { @@ -20,7 +20,7 @@ switch (*plltype) { --- a/drivers/ssb/driver_mipscore.c +++ b/drivers/ssb/driver_mipscore.c -@@ -161,6 +161,8 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m +@@ -217,6 +217,8 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) { rate = 200000000; @@ -31,7 +31,7 @@ } --- a/drivers/ssb/main.c +++ b/drivers/ssb/main.c -@@ -1010,6 +1010,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus) +@@ -1073,6 +1073,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus) if (bus->chip_id == 0x5365) { rate = 100000000;