X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/2f3b768d56c443c04e57ada7ac6893ef7c8ab7bc..cf68680797fe79da2bec58026d61f1444fad37b6:/target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c

diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c
index 002aaebab..5916888f0 100644
--- a/target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c
+++ b/target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c
@@ -1,7 +1,7 @@
 /*
  * Ralink RT305x SoC specific setup
  *
- * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
  * Parts of this file are based on Ralink's 2.6.21 BSP
@@ -14,18 +14,12 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/module.h>
-#include <linux/gpio.h>
 
 #include <asm/mach-ralink/common.h>
+#include <asm/mach-ralink/ramips_gpio.h>
 #include <asm/mach-ralink/rt305x.h>
 #include <asm/mach-ralink/rt305x_regs.h>
 
-unsigned long rt305x_cpu_freq;
-EXPORT_SYMBOL_GPL(rt305x_cpu_freq);
-
-unsigned long rt305x_sys_freq;
-EXPORT_SYMBOL_GPL(rt305x_sys_freq);
-
 void __iomem * rt305x_sysc_base;
 void __iomem * rt305x_memc_base;
 
@@ -49,24 +43,76 @@ void __init rt305x_detect_sys_type(void)
 		(id & CHIP_ID_REV_MASK));
 }
 
-void __init rt305x_detect_sys_freq(void)
-{
-	u32	t;
-
-	t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG);
-	t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
-
-	switch (t) {
-	case SYSTEM_CONFIG_CPUCLK_320:
-		rt305x_cpu_freq = 320000000;
-		break;
-	case SYSTEM_CONFIG_CPUCLK_384:
-		rt305x_cpu_freq = 384000000;
-		break;
-	}
-
-	rt305x_sys_freq = rt305x_cpu_freq / 3;
-}
+static struct ramips_gpio_chip rt305x_gpio_chips[] = {
+	{
+		.chip = {
+			.label	= "RT305X-GPIO0",
+			.base	= 0,
+			.ngpio	= 24,
+		},
+		.regs = {
+			[RAMIPS_GPIO_REG_INT]	= 0x00,
+			[RAMIPS_GPIO_REG_EDGE]	= 0x04,
+			[RAMIPS_GPIO_REG_RENA]	= 0x08,
+			[RAMIPS_GPIO_REG_FENA]	= 0x0c,
+			[RAMIPS_GPIO_REG_DATA]	= 0x20,
+			[RAMIPS_GPIO_REG_DIR]	= 0x24,
+			[RAMIPS_GPIO_REG_POL]	= 0x28,
+			[RAMIPS_GPIO_REG_SET]	= 0x2c,
+			[RAMIPS_GPIO_REG_RESET]	= 0x30,
+			[RAMIPS_GPIO_REG_TOGGLE] = 0x34,
+		},
+		.map_base = RT305X_PIO_BASE,
+		.map_size = RT305X_PIO_SIZE,
+	},
+	{
+		.chip = {
+			.label	= "RT305X-GPIO1",
+			.base	= 24,
+			.ngpio	= 16,
+		},
+		.regs = {
+			[RAMIPS_GPIO_REG_INT]	= 0x38,
+			[RAMIPS_GPIO_REG_EDGE]	= 0x3c,
+			[RAMIPS_GPIO_REG_RENA]	= 0x40,
+			[RAMIPS_GPIO_REG_FENA]	= 0x44,
+			[RAMIPS_GPIO_REG_DATA]	= 0x48,
+			[RAMIPS_GPIO_REG_DIR]	= 0x4c,
+			[RAMIPS_GPIO_REG_POL]	= 0x50,
+			[RAMIPS_GPIO_REG_SET]	= 0x54,
+			[RAMIPS_GPIO_REG_RESET]	= 0x58,
+			[RAMIPS_GPIO_REG_TOGGLE] = 0x5c,
+		},
+		.map_base = RT305X_PIO_BASE,
+		.map_size = RT305X_PIO_SIZE,
+	},
+	{
+		.chip = {
+			.label	= "RT305X-GPIO2",
+			.base	= 40,
+			.ngpio	= 12,
+		},
+		.regs = {
+			[RAMIPS_GPIO_REG_INT]	= 0x60,
+			[RAMIPS_GPIO_REG_EDGE]	= 0x64,
+			[RAMIPS_GPIO_REG_RENA]	= 0x68,
+			[RAMIPS_GPIO_REG_FENA]	= 0x6c,
+			[RAMIPS_GPIO_REG_DATA]	= 0x70,
+			[RAMIPS_GPIO_REG_DIR]	= 0x74,
+			[RAMIPS_GPIO_REG_POL]	= 0x78,
+			[RAMIPS_GPIO_REG_SET]	= 0x7c,
+			[RAMIPS_GPIO_REG_RESET]	= 0x80,
+			[RAMIPS_GPIO_REG_TOGGLE] = 0x84,
+		},
+		.map_base = RT305X_PIO_BASE,
+		.map_size = RT305X_PIO_SIZE,
+	},
+};
+
+static struct ramips_gpio_data rt305x_gpio_data = {
+	.chips = rt305x_gpio_chips,
+	.num_chips = ARRAY_SIZE(rt305x_gpio_chips),
+};
 
 static void rt305x_gpio_reserve(int first, int last)
 {
@@ -80,7 +126,7 @@ void __init rt305x_gpio_init(u32 mode)
 
 	rt305x_sysc_wr(mode, SYSC_REG_GPIO_MODE);
 
-	ramips_gpio_init();
+	ramips_gpio_init(&rt305x_gpio_data);
 	if ((mode & RT305X_GPIO_MODE_I2C) == 0)
 		rt305x_gpio_reserve(RT305X_GPIO_I2C_SD, RT305X_GPIO_I2C_SCLK);