X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/33a352a75bf0d2246368dd07be2a0607af6004ba..fd472b607b89337bf1a6caa3d8ce5c380686eb0c:/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c?ds=inline

diff --git a/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c b/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c
index 333f64fe6..475009cdd 100644
--- a/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c
+++ b/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c
@@ -37,10 +37,8 @@
 #define RT2880_PCI_REG_SUBID		0x38
 #define RT2880_PCI_REG_ARBCTL		0x80
 
-#define PCI_ACCESS_READ  0
-#define PCI_ACCESS_WRITE 1
-
-void __iomem *rt2880_pci_base;
+static void __iomem *rt2880_pci_base;
+static DEFINE_SPINLOCK(rt2880_pci_lock);
 
 static u32 rt2880_pci_reg_read(u32 reg)
 {
@@ -52,36 +50,39 @@ static void rt2880_pci_reg_write(u32 val, u32 reg)
 	writel(val, rt2880_pci_base + reg);
 }
 
-static void config_access(unsigned char access_type, struct pci_bus *bus,
-			  unsigned int devfn, unsigned char where, u32 *data)
+static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
+					 unsigned int func, unsigned int where)
 {
-	unsigned int slot = PCI_SLOT(devfn);
-	unsigned int address;
-	u8 func = PCI_FUNC(devfn);
-
-	address = (bus->number << 16) | (slot << 11) | (func << 8) |
-		  (where & 0xfc) | 0x80000000;
-
-	rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
-	if (access_type == PCI_ACCESS_WRITE)
-		rt2880_pci_reg_write(*data, RT2880_PCI_REG_CONFIG_DATA);
-	else
-		*data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
+	return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
+		0x80000000);
 }
 
 static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
 				  int where, int size, u32 *val)
 {
-	u32 data = 0;
+	unsigned long flags;
+	u32 address;
+	u32 data;
+
+	address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
+					 PCI_FUNC(devfn), where);
 
-	config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
+	spin_lock_irqsave(&rt2880_pci_lock, flags);
+	rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
+	data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
+	spin_unlock_irqrestore(&rt2880_pci_lock, flags);
 
-	if (size == 1)
+	switch (size) {
+	case 1:
 		*val = (data >> ((where & 3) << 3)) & 0xff;
-	else if (size == 2)
+		break;
+	case 2:
 		*val = (data >> ((where & 3) << 3)) & 0xffff;
-	else
+		break;
+	case 4:
 		*val = data;
+		break;
+	}
 
 	return PCIBIOS_SUCCESSFUL;
 }
@@ -89,21 +90,33 @@ static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
 static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
 				   int where, int size, u32 val)
 {
-	u32 data = 0;
+	unsigned long flags;
+	u32 address;
+	u32 data;
+
+	address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
+					 PCI_FUNC(devfn), where);
 
-	if (size == 4) {
+	spin_lock_irqsave(&rt2880_pci_lock, flags);
+	rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
+	data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
+
+	switch (size) {
+	case 1:
+		data = (data & ~(0xff << ((where & 3) << 3))) |
+		       (val << ((where & 3) << 3));
+		break;
+	case 2:
+		data = (data & ~(0xffff << ((where & 3) << 3))) |
+		       (val << ((where & 3) << 3));
+		break;
+	case 4:
 		data = val;
-	} else {
-		config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
-		if (size == 1)
-			data = (data & ~(0xff << ((where & 3) << 3))) |
-			       (val << ((where & 3) << 3));
-		else if (size == 2)
-			data = (data & ~(0xffff << ((where & 3) << 3))) |
-			       (val << ((where & 3) << 3));
+		break;
 	}
 
-	config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data);
+	rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA);
+	spin_unlock_irqrestore(&rt2880_pci_lock, flags);
 
 	return PCIBIOS_SUCCESSFUL;
 }
@@ -133,43 +146,47 @@ static struct pci_controller rt2880_pci_controller = {
 	.io_resource	= &rt2880_pci_mem_resource,
 };
 
-static inline void read_config(unsigned long bus, unsigned long dev,
-			       unsigned long func, unsigned long reg,
-			       unsigned long *val)
+static inline u32 rt2880_pci_read_u32(unsigned long reg)
 {
-	unsigned long address;
+	unsigned long flags;
+	u32 address;
+	u32 ret;
+
+	address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
 
-	address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) |
-		  0x80000000;
+	spin_lock_irqsave(&rt2880_pci_lock, flags);
 	rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
-	*val = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
+	ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
+	spin_unlock_irqrestore(&rt2880_pci_lock, flags);
+
+	return ret;
 }
 
-static inline void write_config(unsigned long bus, unsigned long dev,
-				unsigned long func, unsigned long reg,
-				unsigned long val)
+static inline void rt2880_pci_write_u32(unsigned long reg, u32 val)
 {
-	unsigned long address;
+	unsigned long flags;
+	u32 address;
+
+	address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
 
-	address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) |
-		  0x80000000;
+	spin_lock_irqsave(&rt2880_pci_lock, flags);
 	rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
 	rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
+	spin_unlock_irqrestore(&rt2880_pci_lock, flags);
 }
 
 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
 	u16 cmd;
-	unsigned long val;
 	int irq = -1;
 
 	if (dev->bus->number != 0)
-		return 0;
+		return irq;
 
 	switch (PCI_SLOT(dev->devfn)) {
 	case 0x00:
-		write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
-		read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
+		rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
+		(void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
 		break;
 	case 0x11:
 		irq = RT288X_CPU_IRQ_PCI;
@@ -195,7 +212,6 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 
 static int __init rt2880_pci_init(void)
 {
-	unsigned long val = 0;
 	int i;
 
 	rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
@@ -212,8 +228,9 @@ static int __init rt2880_pci_init(void)
 	rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
 	rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
 	rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
-	write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
-	read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
+
+	rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
+	(void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
 
 	register_pci_controller(&rt2880_pci_controller);
 	return 0;
@@ -224,8 +241,4 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
 	return 0;
 }
 
-struct pci_fixup pcibios_fixups[] = {
-	{0}
-};
-
 arch_initcall(rt2880_pci_init);