X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/3caf3c48cf0c3ef99654636a50e0e3c993d7b052..3b5a6363a0cebe502193f0af8954caf8db8c52f5:/target/linux/ramips/files/arch/mips/ralink/common/setup.c

diff --git a/target/linux/ramips/files/arch/mips/ralink/common/setup.c b/target/linux/ramips/files/arch/mips/ralink/common/setup.c
index e8126b11c..0d6b8d8c9 100644
--- a/target/linux/ramips/files/arch/mips/ralink/common/setup.c
+++ b/target/linux/ramips/files/arch/mips/ralink/common/setup.c
@@ -19,7 +19,6 @@
 
 #include <asm/mach-ralink/common.h>
 #include <asm/mach-ralink/machine.h>
-#include <ralink_soc.h>
 
 unsigned char ramips_sys_type[RAMIPS_SYS_TYPE_LEN];
 
@@ -31,15 +30,16 @@ const char *get_system_type(void)
 static void __init detect_mem_size(void)
 {
 	unsigned long size;
+	void *base;
 
-	for (size = RALINK_SOC_MEM_SIZE_MIN; size < RALINK_SOC_MEM_SIZE_MAX;
+	base = (void *) KSEG1ADDR(detect_mem_size);
+	for (size = ramips_mem_size_min; size < ramips_mem_size_max;
 	     size <<= 1 ) {
-		if (!memcmp(detect_mem_size,
-			    detect_mem_size + size, 1024))
+		if (!memcmp(base, base + size, 1024))
 			break;
 	}
 
-	add_memory_region(RALINK_SOC_SDRAM_BASE, size, BOOT_MEM_RAM);
+	add_memory_region(ramips_mem_base, size, BOOT_MEM_RAM);
 }
 
 void __init ramips_early_serial_setup(int line, unsigned base, unsigned freq,