X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/3d3fc5722ae7243d19741a8b3bf12f79eb831aca..474eca73a833826ab13ce37a9885b787f666025a:/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.c

diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.c
index 1b32a8dee..12a54ed9f 100644
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.c
+++ b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.c
@@ -158,7 +158,7 @@ static int jz_clk_enable_gating(struct clk *clk)
 {
 	if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
 		return -EINVAL;
-	
+
 	jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
 	return 0;
 }
@@ -873,7 +873,24 @@ void jz4740_clock_udc_enable_auto_suspend(void)
 }
 EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend);
 
-int jz_init_clocks(unsigned long ext_rate)
+void jz4740_clock_suspend(void)
+{
+	jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE,
+		JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
+
+	jz_clk_reg_clear_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
+}
+
+void jz4740_clock_resume(void)
+{
+	jz_clk_reg_set_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
+	while ((jz_clk_reg_read(JZ_REG_CLOCK_PLL) & JZ_CLOCK_PLL_STABLE) == 0);
+
+	jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE,
+		JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
+}
+
+int jz4740_clock_init(void)
 {
 	uint32_t val;
 
@@ -883,7 +900,8 @@ int jz_init_clocks(unsigned long ext_rate)
 
 	spin_lock_init(&jz_clock_lock);
 
-	jz_clk_ext.rate = ext_rate;
+	jz_clk_ext.rate = jz4740_clock_bdata.ext_rate;
+	jz_clk_rtc.rate = jz4740_clock_bdata.rtc_rate;
 
 	val = jz_clk_reg_read(JZ_REG_CLOCK_SPI);
 
@@ -904,5 +922,3 @@ int jz_init_clocks(unsigned long ext_rate)
 
 	return 0;
 }
-EXPORT_SYMBOL_GPL(jz_init_clocks);
-