X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/4235b935881181c13ed2ff07627f3acfb9f43ebc..64684c2ee3f651512139ac3b97a843b00cb36de6:/target/linux/ramips/files/drivers/net/ramips_eth.h

diff --git a/target/linux/ramips/files/drivers/net/ramips_eth.h b/target/linux/ramips/files/drivers/net/ramips_eth.h
index 31c4fc08e..ef644c11b 100644
--- a/target/linux/ramips/files/drivers/net/ramips_eth.h
+++ b/target/linux/ramips/files/drivers/net/ramips_eth.h
@@ -105,6 +105,10 @@
 #define RAMIPS_TX_MAX_CNT1		(RAMIPS_PDMA_OFFSET + 0x24)
 #define RAMIPS_TX_CTX_IDX1		(RAMIPS_PDMA_OFFSET + 0x28)
 #define RAMIPS_TX_DTX_IDX1		(RAMIPS_PDMA_OFFSET + 0x2C)
+#define RAMIPS_RX_BASE_PTR0		(RAMIPS_PDMA_OFFSET + 0x30)
+#define RAMIPS_RX_MAX_CNT0		(RAMIPS_PDMA_OFFSET + 0x34)
+#define RAMIPS_RX_CALC_IDX0		(RAMIPS_PDMA_OFFSET + 0x38)
+#define RAMIPS_RX_DRX_IDX0		(RAMIPS_PDMA_OFFSET + 0x3C)
 #define RAMIPS_TX_BASE_PTR2		(RAMIPS_PDMA_OFFSET + 0x40)
 #define RAMIPS_TX_MAX_CNT2		(RAMIPS_PDMA_OFFSET + 0x44)
 #define RAMIPS_TX_CTX_IDX2		(RAMIPS_PDMA_OFFSET + 0x48)
@@ -113,14 +117,37 @@
 #define RAMIPS_TX_MAX_CNT3		(RAMIPS_PDMA_OFFSET + 0x54)
 #define RAMIPS_TX_CTX_IDX3		(RAMIPS_PDMA_OFFSET + 0x58)
 #define RAMIPS_TX_DTX_IDX3		(RAMIPS_PDMA_OFFSET + 0x5C)
-#define RAMIPS_RX_BASE_PTR0		(RAMIPS_PDMA_OFFSET + 0x30)
-#define RAMIPS_RX_MAX_CNT0		(RAMIPS_PDMA_OFFSET + 0x34)
-#define RAMIPS_RX_CALC_IDX0		(RAMIPS_PDMA_OFFSET + 0x38)
-#define RAMIPS_RX_DRX_IDX0		(RAMIPS_PDMA_OFFSET + 0x3C)
-#define RAMIPS_RX_BASE_PTR1		(RAMIPS_PDMA_OFFSET + 0x40)
-#define RAMIPS_RX_MAX_CNT1		(RAMIPS_PDMA_OFFSET + 0x44)
-#define RAMIPS_RX_CALC_IDX1		(RAMIPS_PDMA_OFFSET + 0x48)
-#define RAMIPS_RX_DRX_IDX1		(RAMIPS_PDMA_OFFSET + 0x4C)
+#define RAMIPS_RX_BASE_PTR1		(RAMIPS_PDMA_OFFSET + 0x60)
+#define RAMIPS_RX_MAX_CNT1		(RAMIPS_PDMA_OFFSET + 0x64)
+#define RAMIPS_RX_CALC_IDX1		(RAMIPS_PDMA_OFFSET + 0x68)
+#define RAMIPS_RX_DRX_IDX1		(RAMIPS_PDMA_OFFSET + 0x6C)
+
+/* MDIO_CFG register bits */
+#define RAMIPS_MDIO_CFG_AUTO_POLL_EN	BIT(29)
+#define RAMIPS_MDIO_CFG_GP1_BP_EN	BIT(16)
+#define RAMIPS_MDIO_CFG_GP1_FRC_EN	BIT(15)
+#define RAMIPS_MDIO_CFG_GP1_SPEED_10	(0 << 13)
+#define RAMIPS_MDIO_CFG_GP1_SPEED_100	(1 << 13)
+#define RAMIPS_MDIO_CFG_GP1_SPEED_1000	(2 << 13)
+#define RAMIPS_MDIO_CFG_GP1_DUPLEX	BIT(12)
+#define RAMIPS_MDIO_CFG_GP1_FC_TX	BIT(11)
+#define RAMIPS_MDIO_CFG_GP1_FC_RX	BIT(10)
+#define RAMIPS_MDIO_CFG_GP1_LNK_DWN	BIT(9)
+#define RAMIPS_MDIO_CFG_GP1_AN_FAIL	BIT(8)
+#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_1	(0 << 6)
+#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_2	(1 << 6)
+#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_4	(2 << 6)
+#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_8	(3 << 6)
+#define RAMIPS_MDIO_CFG_TURBO_MII_FREQ	BIT(5)
+#define RAMIPS_MDIO_CFG_TURBO_MII_MODE	BIT(4)
+#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_0	(0 << 2)
+#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_200	(1 << 2)
+#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_400	(2 << 2)
+#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_INV	(3 << 2)
+#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_0	0
+#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_200	1
+#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_400	2
+#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_INV	3
 
 /* uni-cast port */
 #define RAMIPS_GDM1_ICS_EN		BIT(22)
@@ -201,6 +228,11 @@ struct raeth_priv
 
 	spinlock_t		page_lock;
 	struct ramips_eth_platform_data *plat;
+
+	int			speed;
+	int			duplex;
+	int			tx_fc;
+	int			rx_fc;
 };
 
 #endif /* RAMIPS_ETH_H */