X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/43bb8183eb10d86dffd1f9413b8db1a3ea5de0a3..0570263dcb87e59113374b8910c30a30c65239d0:/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c diff --git a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c index 711a10969..5f10d6a65 100644 --- a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c +++ b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c @@ -1,7 +1,7 @@ /* * Atheros AR71xx PCI host controller driver * - * Copyright (C) 2008-2009 Gabor Juhos + * Copyright (C) 2008-2010 Gabor Juhos * Copyright (C) 2008 Imre Kaloz * * Parts of this file are based on Atheros' 2.6.15 BSP @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -38,22 +39,13 @@ static void __iomem *ar71xx_pcicfg_base; static DEFINE_SPINLOCK(ar71xx_pci_lock); +static int ar71xx_pci_fixup_enable; static inline void ar71xx_pci_delay(void) { mdelay(AR71XX_PCI_DELAY); } -static inline u32 ar71xx_pcicfg_rr(unsigned int reg) -{ - return __raw_readl(ar71xx_pcicfg_base + reg); -} - -static inline void ar71xx_pcicfg_wr(unsigned int reg, u32 val) -{ - __raw_writel(val, ar71xx_pcicfg_base + reg); -} - /* Byte lane enable bits */ static u8 ble_table[4][4] = { {0x0, 0xf, 0xf, 0xf}, @@ -92,34 +84,36 @@ static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn, int ar71xx_pci_be_handler(int is_fixup) { + void __iomem *base = ar71xx_pcicfg_base; u32 pci_err; u32 ahb_err; - pci_err = ar71xx_pcicfg_rr(PCI_REG_PCI_ERR) & 3; + pci_err = __raw_readl(base + PCI_REG_PCI_ERR) & 3; if (pci_err) { if (!is_fixup) printk(KERN_ALERT "PCI error %d at PCI addr 0x%x\n", pci_err, - ar71xx_pcicfg_rr(PCI_REG_PCI_ERR_ADDR)); + __raw_readl(base + PCI_REG_PCI_ERR_ADDR)); - ar71xx_pcicfg_wr(PCI_REG_PCI_ERR, pci_err); + __raw_writel(pci_err, base + PCI_REG_PCI_ERR); } - ahb_err = ar71xx_pcicfg_rr(PCI_REG_AHB_ERR) & 1; + ahb_err = __raw_readl(base + PCI_REG_AHB_ERR) & 1; if (ahb_err) { if (!is_fixup) printk(KERN_ALERT "AHB error at AHB address 0x%x\n", - ar71xx_pcicfg_rr(PCI_REG_AHB_ERR_ADDR)); + __raw_readl(base + PCI_REG_AHB_ERR_ADDR)); - ar71xx_pcicfg_wr(PCI_REG_AHB_ERR, ahb_err); + __raw_writel(ahb_err, base + PCI_REG_AHB_ERR); } - return ((ahb_err | pci_err) ? 1 : 0); + return (ahb_err | pci_err) ? 1 : 0; } static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 cmd) { + void __iomem *base = ar71xx_pcicfg_base; u32 addr; addr = ar71xx_pci_bus_addr(bus, devfn, where); @@ -128,9 +122,9 @@ static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, addr); - ar71xx_pcicfg_wr(PCI_REG_CFG_AD, addr); - ar71xx_pcicfg_wr(PCI_REG_CFG_CBE, - cmd | ar71xx_pci_get_ble(where, size, 0)); + __raw_writel(addr, base + PCI_REG_CFG_AD); + __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0), + base + PCI_REG_CFG_CBE); return ar71xx_pci_be_handler(1); } @@ -138,9 +132,11 @@ static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus, static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) { + void __iomem *base = ar71xx_pcicfg_base; static u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0}; unsigned long flags; u32 data; + int retry = 0; int ret; ret = PCIBIOS_SUCCESSFUL; @@ -148,6 +144,7 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d\n", bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); +retry: spin_lock_irqsave(&ar71xx_pci_lock, flags); if (bus->number == 0 && devfn == 0) { @@ -155,8 +152,8 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, t = PCI_CRP_CMD_READ | (where & ~3); - ar71xx_pcicfg_wr(PCI_REG_CRP_AD_CBE, t); - data = ar71xx_pcicfg_rr(PCI_REG_CRP_RDDATA); + __raw_writel(t, base + PCI_REG_CRP_AD_CBE); + data = __raw_readl(base + PCI_REG_CRP_RDDATA); DBG("PCI: rd local cfg, ad_cbe:%08x, data:%08x\n", t, data); @@ -167,7 +164,7 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, PCI_CFG_CMD_READ); if (err == 0) { - data = ar71xx_pcicfg_rr(PCI_REG_CFG_RDDATA); + data = __raw_readl(base + PCI_REG_CFG_RDDATA); } else { ret = PCIBIOS_DEVICE_NOT_FOUND; data = ~0; @@ -181,12 +178,21 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, *value = (data >> (8 * (where & 3))) & mask[size & 7]; + /* + * PCI controller bug: sometimes reads to the PCI_COMMAND register + * return 0xffff, even though the PCI trace shows the correct value. + * Work around this by retrying reads to this register + */ + if (where == PCI_COMMAND && (*value & 0xffff) == 0xffff && retry++ < 2) + goto retry; + return ret; } static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) { + void __iomem *base = ar71xx_pcicfg_base; unsigned long flags; int ret; @@ -206,8 +212,8 @@ static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, DBG("PCI: wr local cfg, ad_cbe:%08x, value:%08x\n", t, value); - ar71xx_pcicfg_wr(PCI_REG_CRP_AD_CBE, t); - ar71xx_pcicfg_wr(PCI_REG_CRP_WRDATA, value); + __raw_writel(t, base + PCI_REG_CRP_AD_CBE); + __raw_writel(value, base + PCI_REG_CRP_WRDATA); } else { int err; @@ -215,7 +221,7 @@ static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, PCI_CFG_CMD_WRITE); if (err == 0) - ar71xx_pcicfg_wr(PCI_REG_CFG_WRDATA, value); + __raw_writel(value, base + PCI_REG_CFG_WRDATA); else ret = PCIBIOS_DEVICE_NOT_FOUND; } @@ -228,6 +234,9 @@ static void ar71xx_pci_fixup(struct pci_dev *dev) { u32 t; + if (!ar71xx_pci_fixup_enable) + return; + if (dev->bus->number != 0 || dev->devfn != 0) return; @@ -296,8 +305,87 @@ static struct pci_controller ar71xx_pci_controller = { .io_resource = &ar71xx_pci_io_resource, }; +static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + void __iomem *base = ar71xx_reset_base; + u32 pending; + + pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & + __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); + + if (pending & PCI_INT_DEV0) + generic_handle_irq(AR71XX_PCI_IRQ_DEV0); + + else if (pending & PCI_INT_DEV1) + generic_handle_irq(AR71XX_PCI_IRQ_DEV1); + + else if (pending & PCI_INT_DEV2) + generic_handle_irq(AR71XX_PCI_IRQ_DEV2); + + else if (pending & PCI_INT_CORE) + generic_handle_irq(AR71XX_PCI_IRQ_CORE); + + else + spurious_interrupt(); +} + +static void ar71xx_pci_irq_unmask(unsigned int irq) +{ + void __iomem *base = ar71xx_reset_base; + u32 t; + + irq -= AR71XX_PCI_IRQ_BASE; + + t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); + __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); + + /* flush write */ + (void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); +} + +static void ar71xx_pci_irq_mask(unsigned int irq) +{ + void __iomem *base = ar71xx_reset_base; + u32 t; + + irq -= AR71XX_PCI_IRQ_BASE; + + t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); + __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); + + /* flush write */ + (void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); +} + +static struct irq_chip ar71xx_pci_irq_chip = { + .name = "AR71XX PCI ", + .mask = ar71xx_pci_irq_mask, + .unmask = ar71xx_pci_irq_unmask, + .mask_ack = ar71xx_pci_irq_mask, +}; + +static void __init ar71xx_pci_irq_init(void) +{ + void __iomem *base = ar71xx_reset_base; + int i; + + __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE); + __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS); + + for (i = AR71XX_PCI_IRQ_BASE; + i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) { + irq_desc[i].status = IRQ_DISABLED; + set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip, + handle_level_irq); + } + + set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar71xx_pci_irq_handler); +} + int __init ar71xx_pcibios_init(void) { + void __iomem *ddr_base = ar71xx_ddr_base; + ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE); ar71xx_pci_delay(); @@ -306,21 +394,25 @@ int __init ar71xx_pcibios_init(void) ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE, AR71XX_PCI_CFG_SIZE); - - ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN0, PCI_WIN0_OFFS); - ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN1, PCI_WIN1_OFFS); - ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN2, PCI_WIN2_OFFS); - ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN3, PCI_WIN3_OFFS); - ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN4, PCI_WIN4_OFFS); - ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN5, PCI_WIN5_OFFS); - ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN6, PCI_WIN6_OFFS); - ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN7, PCI_WIN7_OFFS); + if (ar71xx_pcicfg_base == NULL) + return -ENOMEM; + + __raw_writel(PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0); + __raw_writel(PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1); + __raw_writel(PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2); + __raw_writel(PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3); + __raw_writel(PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4); + __raw_writel(PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5); + __raw_writel(PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6); + __raw_writel(PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7); ar71xx_pci_delay(); /* clear bus errors */ (void)ar71xx_pci_be_handler(1); + ar71xx_pci_fixup_enable = 1; + ar71xx_pci_irq_init(); register_pci_controller(&ar71xx_pci_controller); return 0;