X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/493a9bf37aaef3c6a4725e3496afc0164e23aa9a..6e2911b4f9b43249a3a8783f777e39591d89ef96:/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h

diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
index f3a5d0a7c..e2cc60758 100644
--- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
+++ b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
@@ -15,15 +15,32 @@
 /* Clock Control register */
 #define PERF_CKCTL_REG			0x4
 
+#define CKCTL_6338_ADSLPHY_EN		(1 << 0)
+#define CKCTL_6338_MPI_EN		(1 << 1)
+#define CKCTL_6338_DRAM_EN		(1 << 2)
 #define CKCTL_6338_ENET_EN		(1 << 4)
 #define CKCTL_6338_USBS_EN		(1 << 4)
 #define CKCTL_6338_SAR_EN		(1 << 5)
 #define CKCTL_6338_SPI_EN		(1 << 9)
 
-#define CKCTL_6338_ALL_SAFE_EN		(CKCTL_6338_ENET_EN |		\
+#define CKCTL_6338_ALL_SAFE_EN		(CKCTL_6338_ADSLPHY_EN |	\
+					CKCTL_6338_MPI_EN |		\
+					CKCTL_6338_ENET_EN |		\
 					CKCTL_6338_SAR_EN |		\
 					CKCTL_6338_SPI_EN)
 
+#define CKCTL_6345_CPU_EN		(1 << 0)
+#define CKCTL_6345_BUS_EN		(1 << 1)
+#define CKCTL_6345_EBI_EN		(1 << 2)
+#define CKCTL_6345_UART_EN		(1 << 3)
+#define CKCTL_6345_ADSLPHY_EN		(1 << 4)
+#define CKCTL_6345_ENET_EN		(1 << 7)
+#define CKCTL_6345_USBS_EN		(1 << 8)
+
+#define CKCTL_6345_ALL_SAFE_EN		(CKCTL_6345_ENET_EN |	\
+					CKCTL_6345_USBS_EN |	\
+					CKCTL_6345_ADSLPHY_EN)
+
 #define CKCTL_6348_ADSLPHY_EN		(1 << 0)
 #define CKCTL_6348_MPI_EN		(1 << 1)
 #define CKCTL_6348_SDRAM_EN		(1 << 2)
@@ -72,7 +89,6 @@
 
 /* Interrupt Mask register */
 #define PERF_IRQMASK_REG		0xc
-#define PERF_IRQSTAT_REG		0x10
 
 /* Interrupt Status register */
 #define PERF_IRQSTAT_REG		0x10
@@ -718,6 +734,8 @@
 #define SDRAM_CFG_BANK_SHIFT		13
 #define SDRAM_CFG_BANK_MASK		(1 << SDRAM_CFG_BANK_SHIFT)
 
+#define SDRAM_MEM_REG			0xc
+
 #define SDRAM_PRIO_REG			0x2C
 #define SDRAM_PRIO_MIPS_SHIFT		29
 #define SDRAM_PRIO_MIPS_MASK		(1 << SDRAM_PRIO_MIPS_SHIFT)
@@ -794,8 +812,8 @@
 #define SPI_BCM_6358_SPI_MSG_DATA	0x02
 #define SPI_BCM_6358_SPI_MSG_DATA_SIZE	0x21e
 
-#define SPI_BCM_6358_SPI_RX_FIFO	0x400
-#define SPI_BCM_6358_SPI_RX_FIFO_SIZE	0x220
+#define SPI_BCM_6358_SPI_RX_DATA	0x400
+#define SPI_BCM_6358_SPI_RX_DATA_SIZE	0x220
 
 #define SPI_BCM_6358_SPI_CMD		0x700	/* 16-bits register */
 
@@ -815,17 +833,17 @@
 /* Shared SPI definitions */
 
 /* Message configuration */
-#define SPI_FD_RW			0
-#define SPI_HD_W			1
-#define SPI_HD_R			2
+#define SPI_FD_RW			0x00
+#define SPI_HD_W			0x01
+#define SPI_HD_R			0x02
 #define SPI_BYTE_CNT_SHIFT		0
 #define SPI_MSG_TYPE_SHIFT		14
 
 /* Command */
-#define SPI_CMD_NOOP			0
-#define SPI_CMD_SOFT_RESET		1
-#define SPI_CMD_HARD_RESET		2
-#define SPI_CMD_START_IMMEDIATE		3
+#define SPI_CMD_NOOP			0x01
+#define SPI_CMD_SOFT_RESET		0x02
+#define SPI_CMD_HARD_RESET		0x04
+#define SPI_CMD_START_IMMEDIATE		0x08
 #define SPI_CMD_COMMAND_SHIFT		0
 #define SPI_CMD_COMMAND_MASK		0x000f
 #define SPI_CMD_DEVICE_ID_SHIFT		4
@@ -851,12 +869,14 @@
 #define SPI_SERIAL_BUSY			0x08
 
 /* Clock configuration */
-#define SPI_CLK_0_391MHZ		1
-#define SPI_CLK_0_781MHZ		2 /* default */
-#define SPI_CLK_1_563MHZ		3
-#define SPI_CLK_3_125MHZ		4
-#define SPI_CLK_6_250MHZ		5
-#define SPI_CLK_12_50MHZ		6
+#define SPI_CLK_20MHZ			0x00
+#define SPI_CLK_0_391MHZ		0x01
+#define SPI_CLK_0_781MHZ		0x02 /* default */
+#define SPI_CLK_1_563MHZ		0x03
+#define SPI_CLK_3_125MHZ		0x04
+#define SPI_CLK_6_250MHZ		0x05
+#define SPI_CLK_12_50MHZ		0x06
+#define SPI_CLK_25MHZ			0x07
 #define SPI_CLK_MASK			0x07
 #define SPI_SSOFFTIME_MASK		0x38
 #define SPI_SSOFFTIME_SHIFT		3