X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/4c2865ecebb5e6975d8cbbeaf37b478b7cd75604..59f0b5d7218274f52c546fbf61d3e6c30472632d:/target/linux/ramips/files/arch/mips/ralink/rt288x/devices.c diff --git a/target/linux/ramips/files/arch/mips/ralink/rt288x/devices.c b/target/linux/ramips/files/arch/mips/ralink/rt288x/devices.c index 3b575f620..fd6122f58 100644 --- a/target/linux/ramips/files/arch/mips/ralink/rt288x/devices.c +++ b/target/linux/ramips/files/arch/mips/ralink/rt288x/devices.c @@ -1,7 +1,7 @@ /* * Ralink RT288x SoC platform device registration * - * Copyright (C) 2008 Gabor Juhos + * Copyright (C) 2008-2011 Gabor Juhos * Copyright (C) 2008 Imre Kaloz * * This program is free software; you can redistribute it and/or modify it @@ -14,6 +14,8 @@ #include #include #include +#include +#include #include @@ -154,7 +156,13 @@ static struct platform_device rt288x_eth_device = { void __init rt288x_register_ethernet(void) { - rt288x_eth_data.sys_freq = rt288x_sys_freq; + struct clk *clk; + + clk = clk_get(NULL, "sys"); + if (IS_ERR(clk)) + panic("unable to get SYS clock, err=%ld", PTR_ERR(clk)); + + rt288x_eth_data.sys_freq = clk_get_rate(clk); rt288x_eth_data.reset_fe = rt288x_fe_reset; rt288x_eth_data.min_pkt_len = 64; @@ -163,3 +171,30 @@ void __init rt288x_register_ethernet(void) platform_device_register(&rt288x_eth_device); } + +static struct resource rt288x_wdt_resources[] = { + { + .start = RT2880_TIMER_BASE, + .end = RT2880_TIMER_BASE + RT2880_TIMER_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device rt288x_wdt_device = { + .name = "ramips-wdt", + .id = -1, + .resource = rt288x_wdt_resources, + .num_resources = ARRAY_SIZE(rt288x_wdt_resources), +}; + +void __init rt288x_register_wdt(void) +{ + u32 t; + + /* enable WDT reset output on pin SRAM_CS_N */ + t = rt288x_sysc_rr(SYSC_REG_CLKCFG); + t |= CLKCFG_SRAM_CS_N_WDT; + rt288x_sysc_wr(t, SYSC_REG_CLKCFG); + + platform_device_register(&rt288x_wdt_device); +}