X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/50b63d35910dbfadedd2891588bdc07b5e07d588..097b43c34c6d4d5c07e382cf095d2f3ca1542d0c:/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h index 4d2f7f216..ce9523d3f 100644 --- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h @@ -32,6 +32,8 @@ #define AR71XX_EHCI_SIZE 0x01000000 #define AR71XX_OHCI_BASE 0x1c000000 #define AR71XX_OHCI_SIZE 0x01000000 +#define AR7240_OHCI_BASE 0x1b000000 +#define AR7240_OHCI_SIZE 0x01000000 #define AR71XX_SPI_BASE 0x1f000000 #define AR71XX_SPI_SIZE 0x01000000 @@ -77,8 +79,7 @@ #define AR71XX_PCI_IRQ_BASE 48 #define AR71XX_PCI_IRQ_COUNT 8 -#define AR71XX_CPU_IRQ_PCI (AR71XX_CPU_IRQ_BASE + 2) -#define AR71XX_CPU_IRQ_WMAC (AR71XX_CPU_IRQ_BASE + 2) +#define AR71XX_CPU_IRQ_IP2 (AR71XX_CPU_IRQ_BASE + 2) #define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3) #define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4) #define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5) @@ -111,44 +112,14 @@ enum ar71xx_soc_type { AR71XX_SOC_AR7141, AR71XX_SOC_AR7161, AR71XX_SOC_AR7240, + AR71XX_SOC_AR7241, + AR71XX_SOC_AR7242, AR71XX_SOC_AR9130, AR71XX_SOC_AR9132 }; extern enum ar71xx_soc_type ar71xx_soc; -enum ar71xx_mach_type { - AR71XX_MACH_GENERIC = 0, - AR71XX_MACH_AP81, /* Atheros AP81 */ - AR71XX_MACH_AP83, /* Atheros AP83 */ - AR71XX_MACH_AW_NR580, /* AzureWave AW-NR580 */ - AR71XX_MACH_RB_411, /* MikroTik RouterBOARD 411/411A/411AH */ - AR71XX_MACH_RB_411U, /* MikroTik RouterBOARD 411U */ - AR71XX_MACH_RB_433, /* MikroTik RouterBOARD 433/433AH */ - AR71XX_MACH_RB_433U, /* MikroTik RouterBOARD 433UAH */ - AR71XX_MACH_RB_450, /* MikroTik RouterBOARD 450 */ - AR71XX_MACH_RB_450G, /* MikroTik RouterBOARD 450G */ - AR71XX_MACH_RB_493, /* Mikrotik RouterBOARD 493/493AH */ - AR71XX_MACH_PB42, /* Atheros PB42 */ - AR71XX_MACH_PB44, /* Atheros PB44 */ - AR71XX_MACH_MZK_W04NU, /* Planex MZK-W04NU */ - AR71XX_MACH_MZK_W300NH, /* Planex MZK-W300NH */ - AR71XX_MACH_TEW_632BRP, /* TRENDnet TEW-632BRP */ - AR71XX_MACH_TL_WR741ND, /* TP-LINK TL-WR741ND */ - AR71XX_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */ - AR71XX_MACH_UBNT_LSSR71, /* Ubiquiti LS-SR71 */ - AR71XX_MACH_UBNT_LSX, /* Ubiquiti LSX */ - AR71XX_MACH_UBNT_RS, /* Ubiquiti RouterStation */ - AR71XX_MACH_UBNT_RSPRO, /* Ubiquiti RouterStation Pro */ - AR71XX_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */ - AR71XX_MACH_WNR2000, /* NETGEAR WNR2000 */ - AR71XX_MACH_WP543, /* Compex WP543 */ - AR71XX_MACH_WRT160NL, /* Linksys WRT160NL */ - AR71XX_MACH_WRT400N, /* Linksys WRT400N */ -}; - -extern enum ar71xx_mach_type ar71xx_mach; - /* * PLL block */ @@ -170,6 +141,7 @@ extern enum ar71xx_mach_type ar71xx_mach; #define AR71XX_ETH1_PLL_SHIFT 19 #define AR724X_PLL_REG_CPU_CONFIG 0x00 +#define AR724X_PLL_REG_PCIE_CONFIG 0x18 #define AR724X_PLL_DIV_SHIFT 0 #define AR724X_PLL_DIV_MASK 0x3ff @@ -250,7 +222,25 @@ static inline u32 ar71xx_usb_ctrl_rr(unsigned reg) #define AR71XX_GPIO_COUNT 16 -#define AR724X_GPIO_COUNT 16 +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) +#define AR724X_GPIO_FUNC_SPI_EN BIT(18) +#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) +#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) +#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) +#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) +#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR724X_GPIO_FUNC_UART_EN BIT(1) +#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR724X_GPIO_COUNT 18 #define AR91XX_GPIO_FUNC_WMAC_LED_EN BIT(22) #define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) @@ -280,6 +270,7 @@ static inline u32 ar71xx_gpio_rr(unsigned reg) void ar71xx_gpio_init(void) __init; void ar71xx_gpio_function_enable(u32 mask); void ar71xx_gpio_function_disable(u32 mask); +void ar71xx_gpio_function_setup(u32 set, u32 clear); /* * DDR_CTRL block @@ -299,6 +290,8 @@ void ar71xx_gpio_function_disable(u32 mask); #define AR724X_DDR_REG_FLUSH_GE0 0x7c #define AR724X_DDR_REG_FLUSH_GE1 0x80 +#define AR724X_DDR_REG_FLUSH_USB 0x84 +#define AR724X_DDR_REG_FLUSH_PCIE 0x88 #define AR91XX_DDR_REG_FLUSH_GE0 0x7c #define AR91XX_DDR_REG_FLUSH_GE1 0x80 @@ -356,30 +349,15 @@ void ar71xx_ddr_flush(u32 reg); #define AR724X_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + 0x4000000) #define AR724X_PCI_CFG_SIZE 0x1000 +#define AR724X_PCI_REG_APP 0x00 +#define AR724X_PCI_REG_RESET 0x18 #define AR724X_PCI_REG_INT_STATUS 0x4c #define AR724X_PCI_REG_INT_MASK 0x50 -#define AR724X_PCI_INT_DEV0 BIT(14) - -static inline void ar724x_pci_wr(unsigned reg, u32 val) -{ - void __iomem *base; - - base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE); - __raw_writel(val, base + reg); - iounmap(base); -} - -static inline u32 ar724x_pci_rr(unsigned reg) -{ - void __iomem *base; - u32 ret; +#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0) +#define AR724X_PCI_RESET_LINK_UP BIT(0) - base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE); - ret = __raw_readl(base + reg); - iounmap(base); - return ret; -} +#define AR724X_PCI_INT_DEV0 BIT(14) /* * RESET block @@ -445,13 +423,25 @@ static inline u32 ar724x_pci_rr(unsigned reg) #define RESET_MODULE_USB_OHCI_DLL BIT(6) #define RESET_MODULE_USB_HOST BIT(5) #define RESET_MODULE_USB_PHY BIT(4) +#define RESET_MODULE_USB_OHCI_DLL_7240 BIT(3) #define RESET_MODULE_PCI_BUS BIT(1) #define RESET_MODULE_PCI_CORE BIT(0) -#define REV_ID_MAJOR_MASK 0xf0 -#define REV_ID_MAJOR_AR71XX 0xa0 -#define REV_ID_MAJOR_AR913X 0xb0 -#define REV_ID_MAJOR_AR724X 0xc0 +#define AR724X_RESET_GE1_MDIO BIT(23) +#define AR724X_RESET_GE0_MDIO BIT(22) +#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) +#define AR724X_RESET_PCIE_PHY BIT(7) +#define AR724X_RESET_PCIE BIT(6) +#define AR724X_RESET_USB_HOST BIT(5) +#define AR724X_RESET_USB_PHY BIT(4) +#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) + +#define REV_ID_MAJOR_MASK 0xfff0 +#define REV_ID_MAJOR_AR71XX 0x00a0 +#define REV_ID_MAJOR_AR913X 0x00b0 +#define REV_ID_MAJOR_AR7240 0x00c0 +#define REV_ID_MAJOR_AR7241 0x0100 +#define REV_ID_MAJOR_AR7242 0x1100 #define AR71XX_REV_ID_MINOR_MASK 0x3 #define AR71XX_REV_ID_MINOR_AR7130 0x0 @@ -482,6 +472,7 @@ static inline u32 ar71xx_reset_rr(unsigned reg) void ar71xx_device_stop(u32 mask); void ar71xx_device_start(u32 mask); +int ar71xx_device_stopped(u32 mask); /* * SPI block