X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/57563ffd07c2b88f6bd9625d9913854e41222393..ee10caa56c0094346c12457ae54b0160794a0e6c:/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c

diff --git a/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c b/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c
index b63980619..bf8e36952 100644
--- a/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c
+++ b/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c
@@ -111,10 +111,9 @@ static int ar724x_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 	 * if we set the BAR with proper base address
 	 */
 	if ((where == 0x10) && (size == 4)) {
-		if (ar71xx_soc == AR71XX_SOC_AR7240)
-			ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0xffff);
-		else
-			ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0x1000ffff);
+		u32 val;
+		val = (ar71xx_soc == AR71XX_SOC_AR7240) ? 0xffff : 0x1000ffff;
+		ar724x_pci_write(ar724x_pci_devcfg_base, where, size, val);
 	}
 
 	return PCIBIOS_SUCCESSFUL;
@@ -256,7 +255,8 @@ static int __init ar724x_pci_setup(void)
 		return -ENODEV;
 	}
 
-	if (ar71xx_soc == AR71XX_SOC_AR7241 || ar71xx_soc == AR71XX_SOC_AR7242) {
+	if (ar71xx_soc == AR71XX_SOC_AR7241 ||
+	    ar71xx_soc == AR71XX_SOC_AR7242) {
 		t = __raw_readl(base + AR724X_PCI_REG_APP);
 		t |= BIT(16);
 		__raw_writel(t, base + AR724X_PCI_REG_APP);
@@ -384,12 +384,12 @@ int __init ar724x_pcibios_init(void)
 
 	return 0;
 
- err_unmap_ctrl:
+err_unmap_ctrl:
 	iounmap(ar724x_pci_ctrl_base);
-  err_unmap_devcfg:
+err_unmap_devcfg:
 	iounmap(ar724x_pci_devcfg_base);
- err_unmap_localcfg:
+err_unmap_localcfg:
 	iounmap(ar724x_pci_localcfg_base);
- err:
+err:
 	return ret;
 }