X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/6638b8471f1d867c7e027301cd0bac58e5c951b3..622eabc631f8dac5bc622d8fb28b1931a9684d7f:/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h

diff --git a/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h b/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h
index d185ce531..91adc5bae 100644
--- a/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h
+++ b/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h
@@ -1,40 +1,29 @@
 /*
- *  $Id$
- *
  *  ADM5120 ethernet switch definitions
  *
  *  This header file defines the hardware registers of the ADM5120 SoC
  *  built-in Ethernet switch.
  *
- *  Copyright (C) 2007 OpenWrt.org
- *  Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version 2
- *  of the License, or (at your option) any later version.
+ *  Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
  *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
  *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the
- *  Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
- *  Boston, MA  02110-1301, USA.
  */
 
-#ifndef _ADM5120_SWITCH_H_
-#define _ADM5120_SWITCH_H_
+#ifndef _MACH_ADM5120_SWITCH_H
+#define _MACH_ADM5120_SWITCH_H
 
-#define BIT(at)		(1 << (at))
-#define BITMASK(len)	((1 << (len))-1)
+#ifndef BIT
+#  define BIT(at)	(1 << (at))
+#endif
+#define BITMASK(len)	(BIT(len)-1)
 
 #define SW_READ_REG(r)		__raw_readl( \
-	(void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + SWITCH_REG_ ## r)
+	(void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + r)
 #define SW_WRITE_REG(r, v)	__raw_writel((v), \
-	(void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + SWITCH_REG_ ## r)
+	(void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + r)
 
 /* Switch register offsets */
 #define SWITCH_REG_CODE		0x0000
@@ -164,12 +153,12 @@
 #define MAC_WT0_MWD_SHIFT	1
 #define MAC_WT0_MWD		BIT(1)	/* MAC write done */
 #define MAC_WT0_WFB		BIT(2)	/* Write Filter Bit */
-#define MAC_WT0_WVN_SHIFT	3
+#define MAC_WT0_WVN_SHIFT	3	/* Write Vlan Number shift */
 #define MAC_WT0_WVE		BIT(6)	/* Write VLAN enable */
 #define MAC_WT0_WPMN_SHIFT	7
 #define MAC_WT0_WAF_SHIFT	13	/* Write Age Field shift */
 #define MAC_WT0_WAF_EMPTY	0
-#define MAC_WT0_WAF_STATIC	7
+#define MAC_WT0_WAF_STATIC	7	/* age: static */
 #define MAC_WT0_MAC0_SHIFT	16
 #define MAC_WT0_MAC1_SHIFT	24
 
@@ -247,6 +236,11 @@
 #define GPIO_CONF0_OE_MASK	(0xFF << GPIO_CONF0_OE_SHIFT)
 #define GPIO_CONF0_OV_MASK	(0xFF << GPIO_CONF0_OV_SHIFT)
 
+/* GPIO_CONF2 register bits */
+#define GPIO_CONF2_CSX0		BIT(4)	/* enable CSX0:INTX0 on GPIO 1:2 */
+#define GPIO_CONF2_CSX1		BIT(5)	/* enable CSX1:INTX1 on GPIO 3:4 */
+#define GPIO_CONF2_EW		BIT(6)	/* enable wait state pin for CSX0/1 */
+
 /* INT_STATUS/INT_MASK register bits */
 #define SWITCH_INT_SHD		BIT(0)	/* Send High Done */
 #define SWITCH_INT_SLD		BIT(1)	/* Send Low Done */
@@ -303,4 +297,4 @@
 #define LED1_IV_SHIFT		13	/* LED1 input value shift */
 #define LED2_IV_SHIFT		14	/* LED2 input value shift */
 
-#endif /* _ADM5120_SWITCH_H_ */
+#endif /* _MACH_ADM5120_SWITCH_H */