X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/6ddec82f97677610a82261d7c22cf2dd82b407b5..574f469e143456a4ea1f9f2087d9b7fee72fea8d:/target/linux/ifxmips/files/arch/mips/pci/pci-ifxmips.c?ds=sidebyside

diff --git a/target/linux/ifxmips/files/arch/mips/pci/pci-ifxmips.c b/target/linux/ifxmips/files/arch/mips/pci/pci-ifxmips.c
index bd500bdec..6ff765e85 100644
--- a/target/linux/ifxmips/files/arch/mips/pci/pci-ifxmips.c
+++ b/target/linux/ifxmips/files/arch/mips/pci/pci-ifxmips.c
@@ -4,11 +4,11 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/mm.h>
-#include <asm/ifxmips/ifxmips.h>
-#include <asm/ifxmips/ifxmips_irq.h>
-#include <asm/ifxmips/ifxmips_cgu.h>
 #include <asm/addrspace.h>
 #include <linux/vmalloc.h>
+#include <ifxmips.h>
+#include <ifxmips_irq.h>
+#include <ifxmips_cgu.h>
 
 #define IFXMIPS_PCI_MEM_BASE    0x18000000
 #define IFXMIPS_PCI_MEM_SIZE    0x02000000
@@ -49,8 +49,14 @@ static struct pci_controller ifxmips_pci_controller =
 	.io_offset	= 0x00000000UL,
 };
 
+/* the cpu can can generate the 33Mhz or rely on an external clock the cgu needs the
+   proper setting, otherwise the cpu hangs. we have no way of runtime detecting this */
 u32 ifxmips_pci_mapped_cfg;
-u32 ifxmips_pci_external_clock = 0;
+int ifxmips_pci_external_clock = 0;
+
+/* Since the PCI REQ pins can be reused for other functionality, make it possible
+   to exclude those from interpretation by the PCI controller */
+int ifxmips_pci_req_mask = 0xf;
 
 static int __init
 ifxmips_pci_set_external_clk(char *str)
@@ -87,6 +93,17 @@ pcibios_plat_dev_init(struct pci_dev *dev)
 	return 0;
 }
 
+static u32 calc_bar11mask(void)
+{
+	u32 mem, bar11mask;
+
+	/* BAR11MASK value depends on available memory on system. */
+	mem = num_physpages * PAGE_SIZE;
+	bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) -1)) -1)) | 8;
+
+	return bar11mask;
+}
+
 static void __init
 ifxmips_pci_startup(void)
 {
@@ -113,7 +130,7 @@ ifxmips_pci_startup(void)
 
 	/* enable external 2 PCI masters */
 	temp_buffer = ifxmips_r32(PCI_CR_PC_ARB);
-	temp_buffer &= (~(0xf << 16));
+	temp_buffer &= (~(ifxmips_pci_req_mask << 16));
 	/* enable internal arbiter */
 	temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
 	/* enable internal PCI master reqest */
@@ -136,7 +153,7 @@ ifxmips_pci_startup(void)
 	ifxmips_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
 	ifxmips_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
 	ifxmips_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
-	ifxmips_w32(0x0e000008, PCI_CR_BAR11MASK);
+	ifxmips_w32(calc_bar11mask(), PCI_CR_BAR11MASK);
 	ifxmips_w32(0, PCI_CR_PCI_ADDR_MAP11);
 	ifxmips_w32(0, PCI_CS_BASE_ADDR1);
 #ifdef CONFIG_SWAP_IO_SPACE
@@ -173,7 +190,7 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
 	}
 }
 
-int
+int __init
 pcibios_init(void)
 {
 	extern int pci_probe_only;
@@ -181,7 +198,6 @@ pcibios_init(void)
 	pci_probe_only = 0;
 	printk("PCI: Probing PCI hardware on host bus 0.\n");
 	ifxmips_pci_startup ();
-	//	IFXMIPS_PCI_REG32(PCI_CR_CLK_CTRL_REG) &= (~8);
 	ifxmips_pci_mapped_cfg = (u32)ioremap_nocache(0x17000000, 0x800 * 16);
 	printk("IFXMips PCI mapped to 0x%08lX\n", (unsigned long)ifxmips_pci_mapped_cfg);
 	ifxmips_pci_controller.io_map_base = (unsigned long)ioremap(IFXMIPS_PCI_IO_BASE, IFXMIPS_PCI_IO_SIZE - 1);