X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/7072b1e24093a7d70ae52f63386b3639831a87c8..93b9f41b61873dd2e47ddb1446863ac8ca906c94:/target/linux/generic/patches-2.6.39/020-ssb_update.patch?ds=sidebyside diff --git a/target/linux/generic/patches-2.6.39/020-ssb_update.patch b/target/linux/generic/patches-2.6.39/020-ssb_update.patch index 1ee3ad955..8e4ac19ab 100644 --- a/target/linux/generic/patches-2.6.39/020-ssb_update.patch +++ b/target/linux/generic/patches-2.6.39/020-ssb_update.patch @@ -587,6 +587,17 @@ { int err; +@@ -1001,8 +1002,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32 + switch (plltype) { + case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ + if (m & SSB_CHIPCO_CLK_T6_MMASK) +- return SSB_CHIPCO_CLK_T6_M0; +- return SSB_CHIPCO_CLK_T6_M1; ++ return SSB_CHIPCO_CLK_T6_M1; ++ return SSB_CHIPCO_CLK_T6_M0; + case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ + case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ + case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ @@ -1117,23 +1118,22 @@ static u32 ssb_tmslow_reject_bitmask(str { u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV; @@ -749,15 +760,16 @@ return 1; } #endif /* CONFIG_SSB_PCIHOST */ -@@ -307,7 +310,7 @@ int ssb_bus_scan(struct ssb_bus *bus, +@@ -307,8 +310,7 @@ int ssb_bus_scan(struct ssb_bus *bus, } else { if (bus->bustype == SSB_BUSTYPE_PCI) { bus->chip_id = pcidev_to_chipid(bus->host_pci); - pci_read_config_word(bus->host_pci, PCI_REVISION_ID, -+ pci_read_config_byte(bus->host_pci, PCI_REVISION_ID, - &bus->chip_rev); +- &bus->chip_rev); ++ bus->chip_rev = bus->host_pci->revision; bus->chip_package = 0; } else { + bus->chip_id = 0x4710; --- a/drivers/ssb/sprom.c +++ b/drivers/ssb/sprom.c @@ -17,7 +17,7 @@