X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/7571fae3abbeefc6eb9f6dd243edb04a589bd122..2b0cd69920820acb059961d1dc8e0f7ba1977b49:/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c

diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c b/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c
index b13181845..16cb4f1c3 100644
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c
@@ -206,6 +206,36 @@ static void __init ar71xx_mii_ctrl_set_if(unsigned int reg,
 	iounmap(base);
 }
 
+static void ar71xx_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
+{
+	void __iomem *base;
+	unsigned int mii_speed;
+	u32 t;
+
+	switch (speed) {
+	case SPEED_10:
+		mii_speed =  MII_CTRL_SPEED_10;
+		break;
+	case SPEED_100:
+		mii_speed =  MII_CTRL_SPEED_100;
+		break;
+	case SPEED_1000:
+		mii_speed =  MII_CTRL_SPEED_1000;
+		break;
+	default:
+		BUG();
+	}
+
+	base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
+
+	t = __raw_readl(base + reg);
+	t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
+	t |= mii_speed  << MII_CTRL_SPEED_SHIFT;
+	__raw_writel(t, base + reg);
+
+	iounmap(base);
+}
+
 void __init ar71xx_add_device_mdio(unsigned int id, u32 phy_mask)
 {
 	struct platform_device *mdio_dev;
@@ -321,6 +351,7 @@ static void ar71xx_set_speed_ge0(int speed)
 
 	ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
 			val, AR71XX_ETH0_PLL_SHIFT);
+	ar71xx_mii_ctrl_set_speed(MII_REG_MII0_CTRL, speed);
 }
 
 static void ar71xx_set_speed_ge1(int speed)
@@ -329,6 +360,7 @@ static void ar71xx_set_speed_ge1(int speed)
 
 	ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
 			 val, AR71XX_ETH1_PLL_SHIFT);
+	ar71xx_mii_ctrl_set_speed(MII_REG_MII1_CTRL, speed);
 }
 
 static void ar724x_set_speed_ge0(int speed)
@@ -357,6 +389,7 @@ static void ar91xx_set_speed_ge0(int speed)
 
 	ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
 			 val, AR91XX_ETH0_PLL_SHIFT);
+	ar71xx_mii_ctrl_set_speed(MII_REG_MII0_CTRL, speed);
 }
 
 static void ar91xx_set_speed_ge1(int speed)
@@ -365,6 +398,7 @@ static void ar91xx_set_speed_ge1(int speed)
 
 	ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
 			 val, AR91XX_ETH1_PLL_SHIFT);
+	ar71xx_mii_ctrl_set_speed(MII_REG_MII1_CTRL, speed);
 }
 
 static void ar933x_set_speed_ge0(int speed)
@@ -443,11 +477,6 @@ static struct resource ar71xx_eth0_resources[] = {
 		.flags	= IORESOURCE_MEM,
 		.start	= AR71XX_GE0_BASE,
 		.end	= AR71XX_GE0_BASE + 0x200 - 1,
-	}, {
-		.name	= "mii_ctrl",
-		.flags	= IORESOURCE_MEM,
-		.start	= AR71XX_MII_BASE + MII_REG_MII0_CTRL,
-		.end	= AR71XX_MII_BASE + MII_REG_MII0_CTRL + 3,
 	}, {
 		.name	= "mac_irq",
 		.flags	= IORESOURCE_IRQ,
@@ -476,11 +505,6 @@ static struct resource ar71xx_eth1_resources[] = {
 		.flags	= IORESOURCE_MEM,
 		.start	= AR71XX_GE1_BASE,
 		.end	= AR71XX_GE1_BASE + 0x200 - 1,
-	}, {
-		.name	= "mii_ctrl",
-		.flags	= IORESOURCE_MEM,
-		.start	= AR71XX_MII_BASE + MII_REG_MII1_CTRL,
-		.end	= AR71XX_MII_BASE + MII_REG_MII1_CTRL + 3,
 	}, {
 		.name	= "mac_irq",
 		.flags	= IORESOURCE_IRQ,
@@ -742,30 +766,39 @@ void __init ar71xx_add_device_eth(unsigned int id)
 
 	switch (ar71xx_soc) {
 	case AR71XX_SOC_AR7130:
-		pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
-				      : ar71xx_ddr_flush_ge0;
-		pdata->set_speed = id ? ar71xx_set_speed_ge1
-				      : ar71xx_set_speed_ge0;
+		if (id == 0) {
+			pdata->ddr_flush = ar71xx_ddr_flush_ge0;
+			pdata->set_speed = ar71xx_set_speed_ge0;
+		} else {
+			pdata->ddr_flush = ar71xx_ddr_flush_ge1;
+			pdata->set_speed = ar71xx_set_speed_ge1;
+		}
 		break;
 
 	case AR71XX_SOC_AR7141:
 	case AR71XX_SOC_AR7161:
-		pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
-				      : ar71xx_ddr_flush_ge0;
-		pdata->set_speed = id ? ar71xx_set_speed_ge1
-				      : ar71xx_set_speed_ge0;
+		if (id == 0) {
+			pdata->ddr_flush = ar71xx_ddr_flush_ge0;
+			pdata->set_speed = ar71xx_set_speed_ge0;
+		} else {
+			pdata->ddr_flush = ar71xx_ddr_flush_ge1;
+			pdata->set_speed = ar71xx_set_speed_ge1;
+		}
 		pdata->has_gbit = 1;
 		break;
 
 	case AR71XX_SOC_AR7242:
-		ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO |
-					      RESET_MODULE_GE0_PHY;
-		ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO |
-					      RESET_MODULE_GE1_PHY;
-		pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
-				      : ar724x_ddr_flush_ge0;
-		pdata->set_speed = id ? ar724x_set_speed_ge1
-				      : ar7242_set_speed_ge0;
+		if (id == 0) {
+			pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
+					    RESET_MODULE_GE0_PHY;
+			pdata->ddr_flush = ar724x_ddr_flush_ge0;
+			pdata->set_speed = ar7242_set_speed_ge0;
+		} else {
+			pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
+					    RESET_MODULE_GE1_PHY;
+			pdata->ddr_flush = ar724x_ddr_flush_ge1;
+			pdata->set_speed = ar724x_set_speed_ge1;
+		}
 		pdata->has_gbit = 1;
 		pdata->is_ar724x = 1;
 
@@ -778,16 +811,28 @@ void __init ar71xx_add_device_eth(unsigned int id)
 		break;
 
 	case AR71XX_SOC_AR7241:
-		ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO;
-		ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO;
+		if (id == 0)
+			pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
+		else
+			pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
 		/* fall through */
 	case AR71XX_SOC_AR7240:
-		ar71xx_eth0_data.reset_bit |= RESET_MODULE_GE0_PHY;
-		ar71xx_eth1_data.reset_bit |= RESET_MODULE_GE1_PHY;
-		pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
-				      : ar724x_ddr_flush_ge0;
-		pdata->set_speed = id ? ar724x_set_speed_ge1
-				      : ar724x_set_speed_ge0;
+		if (id == 0) {
+			pdata->reset_bit |= RESET_MODULE_GE0_PHY;
+			pdata->ddr_flush = ar724x_ddr_flush_ge0;
+			pdata->set_speed = ar724x_set_speed_ge0;
+
+			pdata->phy_mask = BIT(4);
+		} else {
+			pdata->reset_bit |= RESET_MODULE_GE1_PHY;
+			pdata->ddr_flush = ar724x_ddr_flush_ge1;
+			pdata->set_speed = ar724x_set_speed_ge1;
+
+			pdata->speed = SPEED_1000;
+			pdata->duplex = DUPLEX_FULL;
+			pdata->has_ar7240_switch = 1;
+		}
+		pdata->has_gbit = 1;
 		pdata->is_ar724x = 1;
 		if (ar71xx_soc == AR71XX_SOC_AR7240)
 			pdata->is_ar7240 = 1;
@@ -801,32 +846,46 @@ void __init ar71xx_add_device_eth(unsigned int id)
 		break;
 
 	case AR71XX_SOC_AR9130:
-		pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
-				      : ar91xx_ddr_flush_ge0;
-		pdata->set_speed = id ? ar91xx_set_speed_ge1
-				      : ar91xx_set_speed_ge0;
+		if (id == 0) {
+			pdata->ddr_flush = ar91xx_ddr_flush_ge0;
+			pdata->set_speed = ar91xx_set_speed_ge0;
+		} else {
+			pdata->ddr_flush = ar91xx_ddr_flush_ge1;
+			pdata->set_speed = ar91xx_set_speed_ge1;
+		}
 		pdata->is_ar91xx = 1;
 		break;
 
 	case AR71XX_SOC_AR9132:
-		pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
-				      : ar91xx_ddr_flush_ge0;
-		pdata->set_speed = id ? ar91xx_set_speed_ge1
-				      : ar91xx_set_speed_ge0;
+		if (id == 0) {
+			pdata->ddr_flush = ar91xx_ddr_flush_ge0;
+			pdata->set_speed = ar91xx_set_speed_ge0;
+		} else {
+			pdata->ddr_flush = ar91xx_ddr_flush_ge1;
+			pdata->set_speed = ar91xx_set_speed_ge1;
+		}
 		pdata->is_ar91xx = 1;
 		pdata->has_gbit = 1;
 		break;
 
 	case AR71XX_SOC_AR9330:
 	case AR71XX_SOC_AR9331:
-		ar71xx_eth0_data.reset_bit = AR933X_RESET_GE0_MAC |
-					     AR933X_RESET_GE0_MDIO;
-		ar71xx_eth1_data.reset_bit = AR933X_RESET_GE1_MAC |
-					     AR933X_RESET_GE1_MDIO;
-		pdata->ddr_flush = id ? ar933x_ddr_flush_ge1
-				      : ar933x_ddr_flush_ge0;
-		pdata->set_speed = id ? ar933x_set_speed_ge1
-				      : ar933x_set_speed_ge0;
+		if (id == 0) {
+			pdata->reset_bit = AR933X_RESET_GE0_MAC |
+					   AR933X_RESET_GE0_MDIO;
+			pdata->ddr_flush = ar933x_ddr_flush_ge0;
+			pdata->set_speed = ar933x_set_speed_ge0;
+		} else {
+			pdata->reset_bit = AR933X_RESET_GE1_MAC |
+					   AR933X_RESET_GE1_MDIO;
+			pdata->ddr_flush = ar933x_ddr_flush_ge1;
+			pdata->set_speed = ar933x_set_speed_ge1;
+
+			pdata->speed = SPEED_1000;
+			pdata->duplex = DUPLEX_FULL;
+			pdata->has_ar7240_switch = 1;
+		}
+
 		pdata->has_gbit = 1;
 		pdata->is_ar724x = 1;
 
@@ -841,14 +900,18 @@ void __init ar71xx_add_device_eth(unsigned int id)
 	case AR71XX_SOC_AR9341:
 	case AR71XX_SOC_AR9342:
 	case AR71XX_SOC_AR9344:
-		ar71xx_eth0_data.reset_bit = AR934X_RESET_GE0_MAC |
-					     AR934X_RESET_GE0_MDIO;
-		ar71xx_eth1_data.reset_bit = AR934X_RESET_GE1_MAC |
-					     AR934X_RESET_GE1_MDIO;
-		pdata->ddr_flush = id ? ar934x_ddr_flush_ge1
-				      : ar934x_ddr_flush_ge0;
-		pdata->set_speed = id ? ar934x_set_speed_ge1
-				      : ar934x_set_speed_ge0;
+		if (id == 0) {
+			pdata->reset_bit = AR934X_RESET_GE0_MAC |
+					   AR934X_RESET_GE0_MDIO;
+			pdata->ddr_flush =ar934x_ddr_flush_ge0;
+			pdata->set_speed = ar934x_set_speed_ge0;
+		} else {
+			pdata->reset_bit = AR934X_RESET_GE1_MAC |
+					   AR934X_RESET_GE1_MDIO;
+			pdata->ddr_flush = ar934x_ddr_flush_ge1;
+			pdata->set_speed = ar934x_set_speed_ge1;
+		}
+
 		pdata->has_gbit = 1;
 		pdata->is_ar724x = 1;