X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/789ea10d57657ce479bbdf3d0e2dd9264510faaa..8fb9ab479d4b4df9d66ea4f2f92fa7cf7ff43db5:/target/linux/ramips/files/arch/mips/ralink/common/setup.c diff --git a/target/linux/ramips/files/arch/mips/ralink/common/setup.c b/target/linux/ramips/files/arch/mips/ralink/common/setup.c index 988965bc7..3030fcd15 100644 --- a/target/linux/ramips/files/arch/mips/ralink/common/setup.c +++ b/target/linux/ramips/files/arch/mips/ralink/common/setup.c @@ -12,14 +12,18 @@ #include #include #include +#include #include #include +#include #include +#include #include unsigned char ramips_sys_type[RAMIPS_SYS_TYPE_LEN]; +enum ramips_mach_type ramips_mach = RAMIPS_MACH_GENERIC; const char *get_system_type(void) { @@ -40,6 +44,30 @@ static void __init detect_mem_size(void) add_memory_region(RALINK_SOC_SDRAM_BASE, size, BOOT_MEM_RAM); } +void __init ramips_early_serial_setup(int line, unsigned base, unsigned freq, + unsigned irq) +{ + struct uart_port p; + int err; + + memset(&p, 0, sizeof(p)); + p.flags = UPF_SKIP_TEST; + p.iotype = UPIO_AU; + p.uartclk = freq; + p.regshift = 2; + p.type = PORT_16550A; + + p.mapbase = base; + p.membase = ioremap_nocache(p.mapbase, PAGE_SIZE); + p.line = line; + p.irq = irq; + + err = early_serial_setup(&p); + if (err) + printk(KERN_ERR "early serial%d registration failed %d\n", + line, err); +} + void __init plat_mem_setup(void) { set_io_port_base(KSEG1); @@ -47,3 +75,17 @@ void __init plat_mem_setup(void) detect_mem_size(); ramips_soc_setup(); } + +static int __init ramips_machine_setup(void) +{ + mips_machine_setup(ramips_mach); + return 0; +} + +arch_initcall(ramips_machine_setup); + +static void __init ramips_generic_init(void) +{ +} + +MIPS_MACHINE(RAMIPS_MACH_GENERIC, "Generic Ralink board", ramips_generic_init);