X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/7f0bb8aeb7d5912b73e073a51377a3d676f62723..fc8502c6311f402f8e53615476dd9ee82efd3a61:/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h

diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
index 19033fc49..198c4bfc0 100644
--- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
@@ -66,9 +66,9 @@
 #define AR71XX_MISC_IRQ_BASE	8
 #define AR71XX_MISC_IRQ_COUNT	8
 #define AR71XX_GPIO_IRQ_BASE	16
-#define AR71XX_GPIO_IRQ_COUNT	16
-#define AR71XX_PCI_IRQ_BASE     32
-#define AR71XX_PCI_IRQ_COUNT	4
+#define AR71XX_GPIO_IRQ_COUNT	32
+#define AR71XX_PCI_IRQ_BASE     48
+#define AR71XX_PCI_IRQ_COUNT	8
 
 #define AR71XX_CPU_IRQ_PCI	(AR71XX_CPU_IRQ_BASE + 2)
 #define AR71XX_CPU_IRQ_WMAC	(AR71XX_CPU_IRQ_BASE + 2)
@@ -92,7 +92,7 @@
 #define AR71XX_PCI_IRQ_DEV0	(AR71XX_PCI_IRQ_BASE + 0)
 #define AR71XX_PCI_IRQ_DEV1	(AR71XX_PCI_IRQ_BASE + 1)
 #define AR71XX_PCI_IRQ_DEV2	(AR71XX_PCI_IRQ_BASE + 2)
-#define AR71XX_PCI_IRQ_CORE	(AR71XX_PCI_IRQ_BASE + 3)
+#define AR71XX_PCI_IRQ_CORE	(AR71XX_PCI_IRQ_BASE + 4)
 
 extern u32 ar71xx_ahb_freq;
 extern u32 ar71xx_cpu_freq;
@@ -103,6 +103,7 @@ enum ar71xx_soc_type {
 	AR71XX_SOC_AR7130,
 	AR71XX_SOC_AR7141,
 	AR71XX_SOC_AR7161,
+	AR71XX_SOC_AR7240,
 	AR71XX_SOC_AR9130,
 	AR71XX_SOC_AR9132
 };
@@ -389,16 +390,25 @@ void ar71xx_ddr_flush(u32 reg);
 #define RESET_MODULE_PCI_BUS		BIT(1)
 #define RESET_MODULE_PCI_CORE		BIT(0)
 
-#define REV_ID_MASK		0xff
-#define REV_ID_CHIP_MASK	0xf3
-#define REV_ID_CHIP_AR7130	0xa0
-#define REV_ID_CHIP_AR7141	0xa1
-#define REV_ID_CHIP_AR7161	0xa2
-#define REV_ID_CHIP_AR9130	0xb0
-#define REV_ID_CHIP_AR9132	0xb1
-
-#define REV_ID_REVISION_MASK	0x3
-#define REV_ID_REVISION_SHIFT	2
+#define REV_ID_MAJOR_MASK	0xf0
+#define REV_ID_MAJOR_AR71XX	0xa0
+#define REV_ID_MAJOR_AR913X	0xb0
+#define REV_ID_MAJOR_AR724X	0xc0
+
+#define AR71XX_REV_ID_MINOR_MASK	0x3
+#define AR71XX_REV_ID_MINOR_AR7130	0x0
+#define AR71XX_REV_ID_MINOR_AR7141	0x1
+#define AR71XX_REV_ID_MINOR_AR7161	0x2
+#define AR71XX_REV_ID_REVISION_MASK	0x3
+#define AR71XX_REV_ID_REVISION_SHIFT	2
+
+#define AR91XX_REV_ID_MINOR_MASK	0x3
+#define AR91XX_REV_ID_MINOR_AR9130	0x0
+#define AR91XX_REV_ID_MINOR_AR9132	0x1
+#define AR91XX_REV_ID_REVISION_MASK	0x3
+#define AR91XX_REV_ID_REVISION_SHIFT	2
+
+#define AR724X_REV_ID_REVISION_MASK	0x3
 
 extern void __iomem *ar71xx_reset_base;