X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/7fff341bb3866a3139a3edbe09c7c07ab9dd56e6..e2b5ab4233779ace4e0160ea6f0a9801b7128053:/target/linux/ar7-2.6/files/arch/mips/ar7/vlynq.c?ds=sidebyside diff --git a/target/linux/ar7-2.6/files/arch/mips/ar7/vlynq.c b/target/linux/ar7-2.6/files/arch/mips/ar7/vlynq.c index 06097556d..5856ece1d 100644 --- a/target/linux/ar7-2.6/files/arch/mips/ar7/vlynq.c +++ b/target/linux/ar7-2.6/files/arch/mips/ar7/vlynq.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #define PER_DEVICE_IRQS 32 @@ -288,7 +289,7 @@ EXPORT_SYMBOL(vlynq_unregister_driver); int vlynq_device_enable(struct vlynq_device *dev) { - u32 val; + u32 div; int result; struct plat_vlynq_ops *ops = dev->dev.platform_data; @@ -299,16 +300,23 @@ int vlynq_device_enable(struct vlynq_device *dev) dev->local->control = 0; dev->remote->control = 0; + div = ar7_dsp_freq() / 62500000; + if(ar7_dsp_freq() / div != 62500000) + { + printk(KERN_WARNING + "VLYNQ: Adjusted requested frequency %d to %d\n", + 62500000, ar7_dsp_freq() / div); + } + + printk("VLYNQ: Setting clock to %d (clock divider %u)\n", ar7_dsp_freq() / div, div); + dev->local->control = VLYNQ_CTRL_CLOCK_DIV((div - 1)) | + VLYNQ_CTRL_CLOCK_INT; +/* + dev->local->control = VLYNQ_CTRL_CLOCK_INT; +*/ if (vlynq_linked(dev)) return vlynq_setup_irq(dev); - for (val = 0; val < 8; val++) { - dev->local->control = VLYNQ_CTRL_CLOCK_DIV(val) | - VLYNQ_CTRL_CLOCK_INT; - if (vlynq_linked(dev)) - return vlynq_setup_irq(dev); - } - return -ENODEV; }