X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/809c03fe4c0f90c640b26e6a2792553b592c68f2..cc7e88fe961c1bfd11f34f00a0f42d9ee45bf94a:/target/linux/xburst/files-2.6.32/arch/mips/jz4740/gpio.c?ds=sidebyside

diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/gpio.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/gpio.c
index 30f83fa09..8a99f4d37 100644
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/gpio.c
+++ b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/gpio.c
@@ -25,6 +25,9 @@
 #include <linux/interrupt.h>
 #include <linux/bitops.h>
 
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
 #define JZ_GPIO_BASE_A (32*0)
 #define JZ_GPIO_BASE_B (32*1)
 #define JZ_GPIO_BASE_C (32*2)
@@ -106,6 +109,7 @@ int jz_gpio_set_function(int gpio, enum jz_gpio_function function)
 		jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
 	} else {
 		jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET);
+		jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
 		switch (function) {
 		case JZ_GPIO_FUNC1:
 			jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
@@ -164,7 +168,8 @@ void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num
 
 	for (i = 0; i < num; ++i, ++request) {
 		jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
-		jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_SET);
+		jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR);
+		jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET);
 	}
 }
 EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend);
@@ -299,6 +304,7 @@ static void jz_gpio_irq_unmask(unsigned int irq)
 	jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_CLEAR);
 };
 
+
 /* TODO: Check if function is gpio */
 static unsigned int jz_gpio_irq_startup(unsigned int irq)
 {
@@ -306,8 +312,8 @@ static unsigned int jz_gpio_irq_startup(unsigned int irq)
 
 	jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_SET);
 
-	jz_gpio_irq_unmask(irq);
 	desc->status &= ~IRQ_MASKED;
+	jz_gpio_irq_unmask(irq);
 
 	return 0;
 }
@@ -431,36 +437,38 @@ static struct jz_gpio_chip jz_gpio_chips[] = {
 	JZ_GPIO_CHIP(D),
 };
 
-static int jz_gpio_suspend(struct sys_device *dev, pm_message_t state)
+int jz_gpio_suspend(void)
 {
 	struct jz_gpio_chip *chip = jz_gpio_chips;
 	int i, gpio;
+
 	for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
 		gpio = chip->gpio_chip.base;
 		chip->suspend_mask = readl(GPIO_TO_REG(gpio, JZ_REG_GPIO_MASK));
 		writel(~(chip->wakeup), GPIO_TO_REG(gpio, JZ_REG_GPIO_MASK_SET));
+		writel(chip->wakeup, GPIO_TO_REG(gpio, JZ_REG_GPIO_MASK_CLEAR));
 	}
 
+	chip = jz_gpio_chips;
+
 	return 0;
 }
 
-static int jz_gpio_resume(struct sys_device *dev)
+int jz_gpio_resume(void)
 {
 	struct jz_gpio_chip *chip = jz_gpio_chips;
 	int i;
+
 	for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
-		writel(~(chip->suspend_mask), GPIO_TO_REG(chip->gpio_chip.base, JZ_REG_GPIO_MASK_CLEAR));
+		writel(~(chip->suspend_mask), GPIO_TO_REG(chip->gpio_chip.base,
+			JZ_REG_GPIO_MASK_CLEAR));
+		writel(chip->suspend_mask, GPIO_TO_REG(chip->gpio_chip.base,
+			JZ_REG_GPIO_MASK_SET));
 	}
 
 	return 0;
 }
 
-static struct sysdev_class jz_gpio_sysdev = {
-	.name = "JZ4740 GPIO",
-	.suspend = jz_gpio_suspend,
-	.resume = jz_gpio_resume,
-};
-
 int __init jz_gpiolib_init(void)
 {
 	struct jz_gpio_chip *chip = jz_gpio_chips;
@@ -480,11 +488,53 @@ int __init jz_gpiolib_init(void)
 		}
 	}
 
-	sysdev_class_register(&jz_gpio_sysdev);
-
 	printk("JZ GPIO initalized\n");
 
 	return 0;
 }
 
+#ifdef CONFIG_DEBUG_FS
+
+static int gpio_regs_show(struct seq_file *s, void *unused)
+{
+	struct jz_gpio_chip *chip = jz_gpio_chips;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
+		seq_printf(s, "GPIO %d: \n", i);
+		seq_printf(s, "\tPin: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_PIN)));
+		seq_printf(s, "\tData: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_DATA)));
+		seq_printf(s, "\tMask: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_MASK)));
+		seq_printf(s, "\tData: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_DATA)));
+		seq_printf(s, "\tPull: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_PULL)));
+		seq_printf(s, "\tFunc: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_FUNC)));
+		seq_printf(s, "\tSelect: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_SELECT)));
+		seq_printf(s, "\tDirection: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_DIRECTION)));
+		seq_printf(s, "\tTrigger: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_TRIGGER)));
+		seq_printf(s, "\tFlag: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_FLAG)));
+	}
+
+	return 0;
+}
+
+static int gpio_regs_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, gpio_regs_show, NULL);
+}
+
+static const struct file_operations gpio_regs_operations = {
+	.open		= gpio_regs_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static int __init gpio_debugfs_init(void)
+{
+	(void) debugfs_create_file("jz_regs_gpio", S_IFREG | S_IRUGO,
+				NULL, NULL, &gpio_regs_operations);
+	return 0;
+}
+subsys_initcall(gpio_debugfs_init);
 
+#endif