X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/843f6cd1fa11357f5d2ef5c0e0bae4f29e491b8b..cc7e88fe961c1bfd11f34f00a0f42d9ee45bf94a:/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.c

diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.c
index 1145921ba..a780706be 100644
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.c
+++ b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.c
@@ -27,9 +27,9 @@
 
 #define JZ_REG_CLOCK_CTRL	0x00
 #define JZ_REG_CLOCK_LOW_POWER	0x04
-#define JZ_REG_CLOCK_SLEEP_CTRL	0x08
 #define JZ_REG_CLOCK_PLL	0x10
 #define JZ_REG_CLOCK_GATE	0x20
+#define JZ_REG_CLOCK_SLEEP_CTRL	0x24
 #define JZ_REG_CLOCK_I2S	0x60
 #define JZ_REG_CLOCK_LCD	0x64
 #define JZ_REG_CLOCK_MMC	0x68
@@ -55,8 +55,8 @@
 #define JZ_CLOCK_GATE_RTC	BIT(2)
 #define JZ_CLOCK_GATE_I2C	BIT(3)
 #define JZ_CLOCK_GATE_SPI	BIT(4)
-#define JZ_CLOCK_GATE_AIC_PCLK	BIT(5)
-#define JZ_CLOCK_GATE_AIC	BIT(6)
+#define JZ_CLOCK_GATE_AIC	BIT(5)
+#define JZ_CLOCK_GATE_I2S	BIT(6)
 #define JZ_CLOCK_GATE_MMC	BIT(7)
 #define JZ_CLOCK_GATE_ADC	BIT(8)
 #define JZ_CLOCK_GATE_CIM	BIT(9)
@@ -158,7 +158,7 @@ static int jz_clk_enable_gating(struct clk *clk)
 {
 	if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
 		return -EINVAL;
-	
+
 	jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
 	return 0;
 }
@@ -626,7 +626,7 @@ static struct divided_clk jz4740_clock_divided_clks[] = {
 		.clk = {
 			.name = "i2s",
 			.parent = &jz_clk_ext.clk,
-			.gate_bit = JZ_CLOCK_GATE_AIC,
+			.gate_bit = JZ_CLOCK_GATE_I2S,
 			.ops = &jz_clk_i2s_ops,
 		},
 		.reg = JZ_REG_CLOCK_I2S,
@@ -721,6 +721,12 @@ static struct clk jz4740_clock_simple_clks[] = {
 		.gate_bit = JZ_CLOCK_GATE_I2C,
 		.ops = &jz_clk_simple_ops,
 	},
+	{
+		.name = "aic",
+		.parent = &jz_clk_ext.clk,
+		.gate_bit = JZ_CLOCK_GATE_AIC,
+		.ops = &jz_clk_simple_ops,
+	},
 };
 
 static struct static_clk jz_clk_rtc = {
@@ -873,7 +879,24 @@ void jz4740_clock_udc_enable_auto_suspend(void)
 }
 EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend);
 
-int jz_init_clocks(unsigned long ext_rate)
+void jz4740_clock_suspend(void)
+{
+	jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE,
+		JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
+
+	jz_clk_reg_clear_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
+}
+
+void jz4740_clock_resume(void)
+{
+	jz_clk_reg_set_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
+	while ((jz_clk_reg_read(JZ_REG_CLOCK_PLL) & JZ_CLOCK_PLL_STABLE) == 0);
+
+	jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE,
+		JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
+}
+
+int jz4740_clock_init(void)
 {
 	uint32_t val;
 
@@ -883,7 +906,8 @@ int jz_init_clocks(unsigned long ext_rate)
 
 	spin_lock_init(&jz_clock_lock);
 
-	jz_clk_ext.rate = ext_rate;
+	jz_clk_ext.rate = jz4740_clock_bdata.ext_rate;
+	jz_clk_rtc.rate = jz4740_clock_bdata.rtc_rate;
 
 	val = jz_clk_reg_read(JZ_REG_CLOCK_SPI);
 
@@ -904,5 +928,3 @@ int jz_init_clocks(unsigned long ext_rate)
 
 	return 0;
 }
-EXPORT_SYMBOL_GPL(jz_init_clocks);
-