X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/8c72b797b421258e17ad6f7afcbc2ab9105e8dc8..e2b5ab4233779ace4e0160ea6f0a9801b7128053:/target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h

diff --git a/target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h b/target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h
index fe51a8d67..49e66ff3a 100644
--- a/target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h
+++ b/target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h
@@ -21,30 +21,36 @@
 #ifndef __AR7_H__
 #define __AR7_H__
 
-#include <asm/addrspace.h>
 #include <linux/delay.h>
+#include <asm/addrspace.h>
+#include <asm/io.h>
 
 #define AR7_REGS_BASE 0x08610000
 
 #define AR7_REGS_MAC0   (AR7_REGS_BASE + 0x0000)
-#define AR7_REGS_EMIF   (AR7_REGS_BASE + 0x0800)
 #define AR7_REGS_GPIO   (AR7_REGS_BASE + 0x0900)
-#define AR7_REGS_POWER  (AR7_REGS_BASE + 0x0a00)
-#define AR7_REGS_WDT    (AR7_REGS_BASE + 0x0b00)
+#define AR7_REGS_POWER  (AR7_REGS_BASE + 0x0a00) // 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock)
 #define AR7_REGS_UART0  (AR7_REGS_BASE + 0x0e00)
-#define AR7_REGS_UART1  (AR7_REGS_BASE + 0x0f00)
 #define AR7_REGS_RESET  (AR7_REGS_BASE + 0x1600)
 #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
+#define AR7_REGS_DCL    (AR7_REGS_BASE + 0x1A00)
 #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1C00)
 #define AR7_REGS_MDIO   (AR7_REGS_BASE + 0x1E00)
 #define AR7_REGS_IRQ    (AR7_REGS_BASE + 0x2400)
 #define AR7_REGS_MAC1   (AR7_REGS_BASE + 0x2800)
 
+#define AR7_REGS_WDT    (AR7_REGS_BASE + 0x1f00)
+#define UR8_REGS_WDT    (AR7_REGS_BASE + 0x0b00)
+#define UR8_REGS_UART1  (AR7_REGS_BASE + 0x0f00)
+
 #define  AR7_RESET_PEREPHERIAL 0x0
 #define  AR7_RESET_SOFTWARE    0x4
 #define  AR7_RESET_STATUS      0x8
 
-#define AR7_RESET_BIT_MDIO   22
+#define AR7_RESET_BIT_CPMAC_LO 17
+#define AR7_RESET_BIT_CPMAC_HI 21
+#define AR7_RESET_BIT_MDIO     22
+#define AR7_RESET_BIT_EPHY     26
 
 /* GPIO control registers */
 #define  AR7_GPIO_INPUT  0x0
@@ -52,8 +58,9 @@
 #define  AR7_GPIO_DIR    0x8
 #define  AR7_GPIO_ENABLE 0xC
 
-#define AR7_GPIO_BIT_STATUS_LED   8
-
+#define AR7_CHIP_7100 0x18
+#define AR7_CHIP_7200 0x2b
+#define AR7_CHIP_7300 0x05
 
 /* Interrupts */
 #define AR7_IRQ_UART0  15
@@ -66,67 +73,69 @@ struct plat_cpmac_data {
 	char dev_addr[6];
 };
 
-extern char *prom_getenv(char *envname);
+struct plat_dsl_data {
+	int reset_bit_dsl;
+	int reset_bit_sar;
+};
+
+extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
 
-/* A bunch of small bit-toggling functions */
-static inline u32 get_chip_id(void)
+static inline u16 ar7_chip_id(void)
 {
-	return *((u16 *)KSEG1ADDR(AR7_REGS_GPIO + 0x14));
+	return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff;
+}
+
+static inline u8 ar7_chip_rev(void)
+{
+	return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
 }
 
 static inline int ar7_cpu_freq(void)
 {
-	u16 chip_id = get_chip_id();
-	switch (chip_id) {
-	case 0x5:
-		return 150000000;
-	case 0x18:
-	case 0x2b:
-		return 211968000;
-	default:
-		return 150000000;
-	}
+	return ar7_cpu_clock;
 }
 
 static inline int ar7_bus_freq(void)
 {
-	u16 chip_id = get_chip_id();
-	switch (chip_id) {
-	case 0x5:
-		return 125000000;
-	case 0x18:
-	case 0x2b:
-		return 105984000;
-	default:
-		return 125000000;
-	}
+	return ar7_bus_clock;
+}
+
+static inline int ar7_vbus_freq(void)
+{
+	return ar7_bus_clock / 2;
+}
+#define ar7_cpmac_freq ar7_vbus_freq
+
+static inline int ar7_dsp_freq(void)
+{
+	return ar7_dsp_clock;
 }
-#define ar7_cpmac_freq ar7_bus_freq
 
 static inline int ar7_has_high_cpmac(void)
 {
-	u16 chip_id = get_chip_id();
+	u16 chip_id = ar7_chip_id();
 	switch (chip_id) {
-	case 0x18:
-	case 0x2b:
+	case AR7_CHIP_7100:
+	case AR7_CHIP_7200:
 		return 0;
 	default:
 		return 1;
 	}
 }
 #define ar7_has_high_vlynq ar7_has_high_cpmac
+#define ar7_has_second_uart ar7_has_high_cpmac
 
 static inline void ar7_device_enable(u32 bit)
 {
-	volatile u32 *reset_reg = (u32 *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
-	*reset_reg |= (1 << bit);	
+	void *reset_reg = (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
+	writel(readl(reset_reg) | (1 << bit), reset_reg);
 	mdelay(20);
 }
 
 static inline void ar7_device_disable(u32 bit)
 {
-	volatile u32 *reset_reg = (u32 *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
-	*reset_reg &= ~(1 << bit);
+	void *reset_reg = (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
+	writel(readl(reset_reg) & ~(1 << bit), reset_reg);
 	mdelay(20);
 }
 
@@ -138,16 +147,16 @@ static inline void ar7_device_reset(u32 bit)
 
 static inline void ar7_device_on(u32 bit)
 {
-	volatile u32 *power_reg = (u32 *)KSEG1ADDR(AR7_REGS_POWER);
-	*power_reg |= (1 << bit);
+	void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
+	writel(readl(power_reg) | (1 << bit), power_reg);
 	mdelay(20);
 }
 
 static inline void ar7_device_off(u32 bit)
 {
-	volatile u32 *power_reg = (u32 *)KSEG1ADDR(AR7_REGS_POWER);
-	*power_reg &= ~(1 << bit);
+	void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
+	writel(readl(power_reg) & ~(1 << bit), power_reg);
 	mdelay(20);
 }
 
-#endif
+#endif /* __AR7_H__ */