X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/8f241d9a09b0dbc2a636a26bcb7e153c8a39f2e1..1d1240855a20a954a108e5692182e9234a1a7f9a:/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h

diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
index 4a732e2af..87a352cc4 100644
--- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
@@ -72,6 +72,8 @@
 
 #define AR933X_UART_BASE	(AR71XX_APB_BASE + 0x00020000)
 #define AR933X_UART_SIZE	0x14
+#define AR933X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
+#define AR933X_GMAC_SIZE	0x04
 #define AR933X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
 #define AR933X_WMAC_SIZE	0x20000
 
@@ -210,6 +212,7 @@ extern enum ar71xx_soc_type ar71xx_soc;
 #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK	0x7
 
 #define AR934X_PLL_REG_CPU_CONFIG	0x00
+#define AR934X_PLL_REG_DDR_CONFIG	0x04
 #define AR934X_PLL_REG_DDR_CTRL_CLOCK	0x8
 
 #define AR934X_CPU_PLL_CFG_OUTDIV_MSB	21
@@ -370,6 +373,13 @@ extern enum ar71xx_soc_type ar71xx_soc;
 
 #define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_RESET	1
 
+#define AR934X_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS		BIT(2)
+#define AR934X_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS		BIT(3)
+#define AR934X_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS		BIT(4)
+#define AR934X_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL	BIT(20)
+#define AR934X_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL	BIT(21)
+#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL	BIT(24)
+
 extern void __iomem *ar71xx_pll_base;
 
 static inline void ar71xx_pll_wr(unsigned reg, u32 val)
@@ -768,6 +778,23 @@ void ar71xx_flash_release(void);
 #define MII1_CTRL_IF_RGMII	0
 #define MII1_CTRL_IF_RMII	1
 
+/*
+ * AR933X GMAC
+ */
+#define AR933X_GMAC_REG_ETH_CFG		0x00
+
+#define AR933X_ETH_CFG_RGMII_GE0	BIT(0)
+#define AR933X_ETH_CFG_MII_GE0		BIT(1)
+#define AR933X_ETH_CFG_GMII_GE0		BIT(2)
+#define AR933X_ETH_CFG_MII_GE0_MASTER	BIT(3)
+#define AR933X_ETH_CFG_MII_GE0_SLAVE	BIT(4)
+#define AR933X_ETH_CFG_MII_GE0_ERR_EN	BIT(5)
+#define AR933X_ETH_CFG_SW_PHY_SWAP	BIT(7)
+#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP	BIT(8)
+#define AR933X_ETH_CFG_RMII_GE0		BIT(9)
+#define AR933X_ETH_CFG_RMII_GE0_SPD_10	0
+#define AR933X_ETH_CFG_RMII_GE0_SPD_100	BIT(10)
+
 #endif /* __ASSEMBLER__ */
 
 #endif /* __ASM_MACH_AR71XX_H */