X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/90fba37c49479ed4e5233dc0d348cdf7d24c9ee1..807dad190f2e9a4fd7651808e33d2d8992c7d700:/target/linux/brcm-2.4/patches/003-bcm47xx_cache_fixes.patch diff --git a/target/linux/brcm-2.4/patches/003-bcm47xx_cache_fixes.patch b/target/linux/brcm-2.4/patches/003-bcm47xx_cache_fixes.patch index 00bd7a7ef..28f8ac48b 100644 --- a/target/linux/brcm-2.4/patches/003-bcm47xx_cache_fixes.patch +++ b/target/linux/brcm-2.4/patches/003-bcm47xx_cache_fixes.patch @@ -1,8 +1,6 @@ -Index: linux-2.4.35.4/arch/mips/kernel/entry.S -=================================================================== ---- linux-2.4.35.4.orig/arch/mips/kernel/entry.S 2007-12-15 05:19:36.266487747 +0100 -+++ linux-2.4.35.4/arch/mips/kernel/entry.S 2007-12-15 05:20:14.372659296 +0100 -@@ -100,6 +100,10 @@ +--- a/arch/mips/kernel/entry.S ++++ b/arch/mips/kernel/entry.S +@@ -100,6 +100,10 @@ END(except_vec1_generic) * and R4400 SC and MC versions. */ NESTED(except_vec3_generic, 0, sp) @@ -13,10 +11,8 @@ Index: linux-2.4.35.4/arch/mips/kernel/entry.S #if R5432_CP0_INTERRUPT_WAR mfc0 k0, CP0_INDEX #endif -Index: linux-2.4.35.4/arch/mips/mm/c-r4k.c -=================================================================== ---- linux-2.4.35.4.orig/arch/mips/mm/c-r4k.c 2007-12-15 05:20:13.948635130 +0100 -+++ linux-2.4.35.4/arch/mips/mm/c-r4k.c 2007-12-15 05:20:14.376659523 +0100 +--- a/arch/mips/mm/c-r4k.c ++++ b/arch/mips/mm/c-r4k.c @@ -14,6 +14,12 @@ #include #include @@ -30,7 +26,7 @@ Index: linux-2.4.35.4/arch/mips/mm/c-r4k.c #include #include #include -@@ -40,6 +46,7 @@ +@@ -40,6 +46,7 @@ static struct bcache_ops no_sc_ops = { .bc_inv = (void *)no_sc_noop }; @@ -38,7 +34,7 @@ Index: linux-2.4.35.4/arch/mips/mm/c-r4k.c struct bcache_ops *bcops = &no_sc_ops; #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x2010) -@@ -64,8 +71,10 @@ +@@ -64,8 +71,10 @@ static inline void r4k_blast_dcache_page static inline void r4k_blast_dcache_page_setup(void) { unsigned long dc_lsize = current_cpu_data.dcache.linesz; @@ -51,7 +47,7 @@ Index: linux-2.4.35.4/arch/mips/mm/c-r4k.c r4k_blast_dcache_page = blast_dcache16_page; else if (dc_lsize == 32) r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; -@@ -77,7 +86,9 @@ +@@ -77,7 +86,9 @@ static void r4k_blast_dcache_page_indexe { unsigned long dc_lsize = current_cpu_data.dcache.linesz; @@ -62,7 +58,7 @@ Index: linux-2.4.35.4/arch/mips/mm/c-r4k.c r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; else if (dc_lsize == 32) r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; -@@ -89,7 +100,9 @@ +@@ -89,7 +100,9 @@ static inline void r4k_blast_dcache_setu { unsigned long dc_lsize = current_cpu_data.dcache.linesz; @@ -73,7 +69,7 @@ Index: linux-2.4.35.4/arch/mips/mm/c-r4k.c r4k_blast_dcache = blast_dcache16; else if (dc_lsize == 32) r4k_blast_dcache = blast_dcache32; -@@ -266,6 +279,7 @@ +@@ -266,6 +279,7 @@ static void r4k___flush_cache_all(void) r4k_blast_dcache(); r4k_blast_icache(); @@ -81,7 +77,7 @@ Index: linux-2.4.35.4/arch/mips/mm/c-r4k.c switch (current_cpu_data.cputype) { case CPU_R4000SC: case CPU_R4000MC: -@@ -304,10 +318,10 @@ +@@ -304,10 +318,10 @@ static void r4k_flush_cache_mm(struct mm * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we * only flush the primary caches but R10000 and R12000 behave sane ... */ @@ -94,7 +90,7 @@ Index: linux-2.4.35.4/arch/mips/mm/c-r4k.c r4k_blast_scache(); } -@@ -383,12 +397,15 @@ +@@ -383,12 +397,15 @@ static void r4k_flush_icache_range(unsig unsigned long ic_lsize = current_cpu_data.icache.linesz; unsigned long addr, aend; @@ -112,7 +108,7 @@ Index: linux-2.4.35.4/arch/mips/mm/c-r4k.c while (1) { /* Hit_Writeback_Inv_D */ -@@ -403,8 +420,6 @@ +@@ -403,8 +420,6 @@ static void r4k_flush_icache_range(unsig if (end - start > icache_size) r4k_blast_icache(); else { @@ -121,7 +117,7 @@ Index: linux-2.4.35.4/arch/mips/mm/c-r4k.c while (1) { /* Hit_Invalidate_I */ protected_flush_icache_line(addr); -@@ -413,6 +428,9 @@ +@@ -413,6 +428,9 @@ static void r4k_flush_icache_range(unsig addr += ic_lsize; } } @@ -131,7 +127,7 @@ Index: linux-2.4.35.4/arch/mips/mm/c-r4k.c } /* -@@ -443,7 +461,8 @@ +@@ -443,7 +461,8 @@ static void r4k_flush_icache_page(struct if (cpu_has_subset_pcaches) { unsigned long addr = (unsigned long) page_address(page); @@ -141,7 +137,7 @@ Index: linux-2.4.35.4/arch/mips/mm/c-r4k.c ClearPageDcacheDirty(page); return; -@@ -451,6 +470,7 @@ +@@ -451,6 +470,7 @@ static void r4k_flush_icache_page(struct if (!cpu_has_ic_fills_f_dc) { unsigned long addr = (unsigned long) page_address(page); @@ -149,7 +145,7 @@ Index: linux-2.4.35.4/arch/mips/mm/c-r4k.c r4k_blast_dcache_page(addr); ClearPageDcacheDirty(page); } -@@ -477,7 +497,7 @@ +@@ -477,7 +497,7 @@ static void r4k_dma_cache_wback_inv(unsi /* Catch bad driver code */ BUG_ON(size == 0); @@ -158,7 +154,7 @@ Index: linux-2.4.35.4/arch/mips/mm/c-r4k.c unsigned long sc_lsize = current_cpu_data.scache.linesz; if (size >= scache_size) { -@@ -509,6 +529,8 @@ +@@ -509,6 +529,8 @@ static void r4k_dma_cache_wback_inv(unsi R4600_HIT_CACHEOP_WAR_IMPL; a = addr & ~(dc_lsize - 1); end = (addr + size - 1) & ~(dc_lsize - 1); @@ -167,7 +163,7 @@ Index: linux-2.4.35.4/arch/mips/mm/c-r4k.c while (1) { flush_dcache_line(a); /* Hit_Writeback_Inv_D */ if (a == end) -@@ -527,7 +549,7 @@ +@@ -527,7 +549,7 @@ static void r4k_dma_cache_inv(unsigned l /* Catch bad driver code */ BUG_ON(size == 0); @@ -176,7 +172,7 @@ Index: linux-2.4.35.4/arch/mips/mm/c-r4k.c unsigned long sc_lsize = current_cpu_data.scache.linesz; if (size >= scache_size) { -@@ -554,6 +576,8 @@ +@@ -554,6 +576,8 @@ static void r4k_dma_cache_inv(unsigned l R4600_HIT_CACHEOP_WAR_IMPL; a = addr & ~(dc_lsize - 1); end = (addr + size - 1) & ~(dc_lsize - 1); @@ -185,7 +181,7 @@ Index: linux-2.4.35.4/arch/mips/mm/c-r4k.c while (1) { flush_dcache_line(a); /* Hit_Writeback_Inv_D */ if (a == end) -@@ -577,6 +601,8 @@ +@@ -577,6 +601,8 @@ static void r4k_flush_cache_sigtramp(uns unsigned long dc_lsize = current_cpu_data.dcache.linesz; R4600_HIT_CACHEOP_WAR_IMPL; @@ -194,7 +190,7 @@ Index: linux-2.4.35.4/arch/mips/mm/c-r4k.c protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); protected_flush_icache_line(addr & ~(ic_lsize - 1)); if (MIPS4K_ICACHE_REFILL_WAR) { -@@ -986,10 +1012,12 @@ +@@ -986,10 +1012,12 @@ static void __init setup_scache(void) case CPU_R4000MC: case CPU_R4400SC: case CPU_R4400MC: @@ -211,7 +207,7 @@ Index: linux-2.4.35.4/arch/mips/mm/c-r4k.c break; case CPU_R10000: -@@ -1041,6 +1069,19 @@ +@@ -1041,6 +1069,19 @@ static void __init setup_scache(void) static inline void coherency_setup(void) { change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); @@ -231,7 +227,7 @@ Index: linux-2.4.35.4/arch/mips/mm/c-r4k.c /* * c0_status.cu=0 specifies that updates by the sc instruction use -@@ -1073,6 +1114,12 @@ +@@ -1073,6 +1114,12 @@ void __init ld_mmu_r4xx0(void) memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80); memcpy((void *)(KSEG1 + 0x100), &except_vec2_generic, 0x80); @@ -244,10 +240,8 @@ Index: linux-2.4.35.4/arch/mips/mm/c-r4k.c probe_pcache(); setup_scache(); -Index: linux-2.4.35.4/arch/mips/mm/tlbex-mips32.S -=================================================================== ---- linux-2.4.35.4.orig/arch/mips/mm/tlbex-mips32.S 2007-12-15 05:19:44.874978317 +0100 -+++ linux-2.4.35.4/arch/mips/mm/tlbex-mips32.S 2007-12-15 05:20:14.380659748 +0100 +--- a/arch/mips/mm/tlbex-mips32.S ++++ b/arch/mips/mm/tlbex-mips32.S @@ -90,6 +90,9 @@ .set noat LEAF(except_vec0_r4000) @@ -258,10 +252,8 @@ Index: linux-2.4.35.4/arch/mips/mm/tlbex-mips32.S #ifdef CONFIG_SMP mfc0 k1, CP0_CONTEXT la k0, pgd_current -Index: linux-2.4.35.4/include/asm-mips/r4kcache.h -=================================================================== ---- linux-2.4.35.4.orig/include/asm-mips/r4kcache.h 2007-12-15 05:20:13.960635812 +0100 -+++ linux-2.4.35.4/include/asm-mips/r4kcache.h 2007-12-15 05:20:14.384659977 +0100 +--- a/include/asm-mips/r4kcache.h ++++ b/include/asm-mips/r4kcache.h @@ -15,6 +15,18 @@ #include #include @@ -309,7 +301,7 @@ Index: linux-2.4.35.4/include/asm-mips/r4kcache.h } static inline void flush_scache_line_indexed(unsigned long addr) -@@ -47,6 +72,7 @@ +@@ -47,6 +72,7 @@ static inline void flush_icache_line(uns static inline void flush_dcache_line(unsigned long addr) { @@ -317,7 +309,7 @@ Index: linux-2.4.35.4/include/asm-mips/r4kcache.h cache_op(Hit_Writeback_Inv_D, addr); } -@@ -91,6 +117,7 @@ +@@ -91,6 +117,7 @@ static inline void protected_flush_icach */ static inline void protected_writeback_dcache_line(unsigned long addr) { @@ -325,7 +317,7 @@ Index: linux-2.4.35.4/include/asm-mips/r4kcache.h __asm__ __volatile__( ".set noreorder\n\t" ".set mips3\n" -@@ -138,6 +165,62 @@ +@@ -138,6 +165,62 @@ static inline void invalidate_tcache_pag : "r" (base), \ "i" (op)); @@ -388,7 +380,7 @@ Index: linux-2.4.35.4/include/asm-mips/r4kcache.h static inline void blast_dcache16(void) { unsigned long start = KSEG0; -@@ -148,8 +231,9 @@ +@@ -148,8 +231,9 @@ static inline void blast_dcache16(void) unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) @@ -399,7 +391,7 @@ Index: linux-2.4.35.4/include/asm-mips/r4kcache.h } static inline void blast_dcache16_page(unsigned long page) -@@ -173,8 +257,9 @@ +@@ -173,8 +257,9 @@ static inline void blast_dcache16_page_i unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) @@ -410,7 +402,7 @@ Index: linux-2.4.35.4/include/asm-mips/r4kcache.h } static inline void blast_icache16(void) -@@ -196,6 +281,7 @@ +@@ -196,6 +281,7 @@ static inline void blast_icache16_page(u unsigned long start = page; unsigned long end = start + PAGE_SIZE; @@ -418,7 +410,7 @@ Index: linux-2.4.35.4/include/asm-mips/r4kcache.h do { cache16_unroll32(start,Hit_Invalidate_I); start += 0x200; -@@ -281,6 +367,7 @@ +@@ -281,6 +367,7 @@ static inline void blast_scache16_page_i : "r" (base), \ "i" (op)); @@ -426,7 +418,7 @@ Index: linux-2.4.35.4/include/asm-mips/r4kcache.h static inline void blast_dcache32(void) { unsigned long start = KSEG0; -@@ -291,8 +378,9 @@ +@@ -291,8 +378,9 @@ static inline void blast_dcache32(void) unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) @@ -437,7 +429,7 @@ Index: linux-2.4.35.4/include/asm-mips/r4kcache.h } static inline void blast_dcache32_page(unsigned long page) -@@ -316,8 +404,9 @@ +@@ -316,8 +404,9 @@ static inline void blast_dcache32_page_i unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) @@ -448,7 +440,7 @@ Index: linux-2.4.35.4/include/asm-mips/r4kcache.h } static inline void blast_icache32(void) -@@ -339,6 +428,7 @@ +@@ -339,6 +428,7 @@ static inline void blast_icache32_page(u unsigned long start = page; unsigned long end = start + PAGE_SIZE; @@ -456,7 +448,7 @@ Index: linux-2.4.35.4/include/asm-mips/r4kcache.h do { cache32_unroll32(start,Hit_Invalidate_I); start += 0x400; -@@ -443,6 +533,7 @@ +@@ -443,6 +533,7 @@ static inline void blast_icache64_page(u unsigned long start = page; unsigned long end = start + PAGE_SIZE; @@ -464,10 +456,8 @@ Index: linux-2.4.35.4/include/asm-mips/r4kcache.h do { cache64_unroll32(start,Hit_Invalidate_I); start += 0x800; -Index: linux-2.4.35.4/include/asm-mips/stackframe.h -=================================================================== ---- linux-2.4.35.4.orig/include/asm-mips/stackframe.h 2007-12-15 05:19:36.298489571 +0100 -+++ linux-2.4.35.4/include/asm-mips/stackframe.h 2007-12-15 05:20:14.388660206 +0100 +--- a/include/asm-mips/stackframe.h ++++ b/include/asm-mips/stackframe.h @@ -209,6 +209,20 @@ #endif @@ -489,11 +479,9 @@ Index: linux-2.4.35.4/include/asm-mips/stackframe.h #define RESTORE_SP \ lw sp, PT_R29(sp); \ -Index: linux-2.4.35.4/mm/memory.c -=================================================================== ---- linux-2.4.35.4.orig/mm/memory.c 2007-12-15 05:19:36.306490026 +0100 -+++ linux-2.4.35.4/mm/memory.c 2007-12-15 05:20:14.388660206 +0100 -@@ -927,6 +927,7 @@ +--- a/mm/memory.c ++++ b/mm/memory.c +@@ -927,6 +927,7 @@ static inline void break_cow(struct vm_a flush_page_to_ram(new_page); flush_cache_page(vma, address); establish_pte(vma, address, page_table, pte_mkwrite(pte_mkdirty(mk_pte(new_page, vma->vm_page_prot))));