X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/a08030216f893563d069fe3f75818581d4a24f34..c132dc87067ddf8607f254642aa3b8c3609783ed:/target/linux/linux-2.4/patches/ar7/000-ar7_support.patch?ds=inline diff --git a/target/linux/linux-2.4/patches/ar7/000-ar7_support.patch b/target/linux/linux-2.4/patches/ar7/000-ar7_support.patch index 45052961e..1930b5754 100644 --- a/target/linux/linux-2.4/patches/ar7/000-ar7_support.patch +++ b/target/linux/linux-2.4/patches/ar7/000-ar7_support.patch @@ -1,7 +1,27 @@ -diff -urN linux.old/arch/mips/ar7/avalanche/avalanche_jump.S linux.dev/arch/mips/ar7/avalanche/avalanche_jump.S ---- linux.old/arch/mips/ar7/avalanche/avalanche_jump.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/avalanche/avalanche_jump.S 2005-07-07 04:39:14.418226000 +0200 -@@ -0,0 +1,69 @@ +diff -urN kernel-base/arch/mips/ar7/ar7/jump.S kernel-current/arch/mips/ar7/ar7/jump.S +--- kernel-base/arch/mips/ar7/ar7/jump.S 1970-01-01 01:00:00.000000000 +0100 ++++ kernel-current/arch/mips/ar7/ar7/jump.S 2005-07-10 06:40:39.582267000 +0200 +@@ -0,0 +1,89 @@ ++/* ++ * $Id$ ++ * Copyright (C) $Date$ $Author$ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ * ++ */ ++ +#include +#include + @@ -71,9 +91,367 @@ diff -urN linux.old/arch/mips/ar7/avalanche/avalanche_jump.S linux.dev/arch/mips +END(jump_dedicated_interrupt) + + .set at -diff -urN linux.old/arch/mips/ar7/avalanche/avalanche_paging.c linux.dev/arch/mips/ar7/avalanche/avalanche_paging.c ---- linux.old/arch/mips/ar7/avalanche/avalanche_paging.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/avalanche/avalanche_paging.c 2005-07-07 04:39:14.418226000 +0200 +diff -urN kernel-base/arch/mips/ar7/ar7/Makefile kernel-current/arch/mips/ar7/ar7/Makefile +--- kernel-base/arch/mips/ar7/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ kernel-current/arch/mips/ar7/ar7/Makefile 2005-07-10 17:46:24.037377984 +0200 +@@ -0,0 +1,31 @@ ++# $Id$ ++# Copyright (C) $Date$ $Author$ ++# ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 2 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ ++.S.s: ++ $(CPP) $(AFLAGS) $< -o $*.s ++ ++.S.o: ++ $(CC) $(AFLAGS) -c $< -o $*.o ++ ++EXTRA_CFLAGS := -DLITTLE_ENDIAN -D_LINK_KSEG0_ ++ ++O_TARGET := ar7.o ++ ++export-objs := misc.o ++obj-y += paging.o jump.o misc.o ++ ++include $(TOPDIR)/Rules.make +diff -urN kernel-base/arch/mips/ar7/ar7/misc.c kernel-current/arch/mips/ar7/ar7/misc.c +--- kernel-base/arch/mips/ar7/ar7/misc.c 1970-01-01 01:00:00.000000000 +0100 ++++ kernel-current/arch/mips/ar7/ar7/misc.c 2005-07-10 19:02:11.699779472 +0200 +@@ -0,0 +1,319 @@ ++#include ++#include ++#include ++#include ++ ++#define TRUE 1 ++ ++static unsigned int avalanche_vbus_freq; ++ ++REMOTE_VLYNQ_DEV_RESET_CTRL_FN p_remote_vlynq_dev_reset_ctrl = NULL; ++ ++/***************************************************************************** ++ * Reset Control Module. ++ *****************************************************************************/ ++void avalanche_reset_ctrl(unsigned int module_reset_bit, ++ AVALANCHE_RESET_CTRL_T reset_ctrl) ++{ ++ volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR; ++ ++ if(module_reset_bit >= 32 && module_reset_bit < 64) ++ return; ++ ++ if(module_reset_bit >= 64) ++ { ++ if(p_remote_vlynq_dev_reset_ctrl) ++ return(p_remote_vlynq_dev_reset_ctrl(module_reset_bit - 64, reset_ctrl)); ++ else ++ return; ++ } ++ ++ if(reset_ctrl == OUT_OF_RESET) ++ *reset_reg |= 1 << module_reset_bit; ++ else ++ *reset_reg &= ~(1 << module_reset_bit); ++} ++ ++AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(unsigned int module_reset_bit) ++{ ++ volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR; ++ ++ return (((*reset_reg) & (1 << module_reset_bit)) ? OUT_OF_RESET : IN_RESET ); ++} ++ ++void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode) ++{ ++ volatile unsigned int *sw_reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_SWRCR; ++ *sw_reset_reg = mode; ++} ++ ++#define AVALANCHE_RST_CTRL_RSR_MASK 0x3 ++ ++AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status() ++{ ++ volatile unsigned int *sys_reset_status = (unsigned int*) AVALANCHE_RST_CTRL_RSR; ++ ++ return ( (AVALANCHE_SYS_RESET_STATUS_T) (*sys_reset_status & AVALANCHE_RST_CTRL_RSR_MASK) ); ++} ++ ++ ++/***************************************************************************** ++ * Power Control Module ++ *****************************************************************************/ ++#define AVALANCHE_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */ ++#define AVALANCHE_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */ ++ ++ ++void avalanche_power_ctrl(unsigned int module_power_bit, AVALANCHE_POWER_CTRL_T power_ctrl) ++{ ++ volatile unsigned int *power_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR; ++ ++ if (power_ctrl == POWER_CTRL_POWER_DOWN) ++ /* power down the module */ ++ *power_reg |= (1 << module_power_bit); ++ else ++ /* power on the module */ ++ *power_reg &= (~(1 << module_power_bit)); ++} ++ ++AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int module_power_bit) ++{ ++ volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR; ++ ++ return (((*power_status_reg) & (1 << module_power_bit)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP); ++} ++ ++void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode) ++{ ++ volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR; ++ ++ *power_status_reg &= AVALANCHE_GLOBAL_POWER_DOWN_MASK; ++ *power_status_reg |= ( power_mode << AVALANCHE_GLOBAL_POWER_DOWN_BIT); ++} ++ ++AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void) ++{ ++ volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR; ++ ++ return((AVALANCHE_SYS_POWER_MODE_T) (((*power_status_reg) & (~AVALANCHE_GLOBAL_POWER_DOWN_MASK)) ++ >> AVALANCHE_GLOBAL_POWER_DOWN_BIT)); ++} ++ ++/***************************************************************************** ++ * GPIO Control ++ *****************************************************************************/ ++ ++/**************************************************************************** ++ * FUNCTION: avalanche_gpio_init ++ ***************************************************************************/ ++void avalanche_gpio_init(void) ++{ ++ spinlock_t closeLock; ++ unsigned int closeFlag; ++ volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR; ++ spin_lock_irqsave(&closeLock, closeFlag); ++ *reset_reg |= (1 << AVALANCHE_GPIO_RESET_BIT); ++ spin_unlock_irqrestore(&closeLock, closeFlag); ++} ++ ++/**************************************************************************** ++ * FUNCTION: avalanche_gpio_ctrl ++ ***************************************************************************/ ++int avalanche_gpio_ctrl(unsigned int gpio_pin, ++ AVALANCHE_GPIO_PIN_MODE_T pin_mode, ++ AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction) ++{ ++ spinlock_t closeLock; ++ unsigned int closeFlag; ++ volatile unsigned int *gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_ENBL; ++ ++ if(gpio_pin >= 32) ++ return(-1); ++ ++ spin_lock_irqsave(&closeLock, closeFlag); ++ ++ if(pin_mode == GPIO_PIN) ++ { ++ *gpio_ctrl |= (1 << gpio_pin); ++ ++ gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_DIR; ++ ++ if(pin_direction == GPIO_INPUT_PIN) ++ *gpio_ctrl |= (1 << gpio_pin); ++ else ++ *gpio_ctrl &= ~(1 << gpio_pin); ++ } ++ else /* FUNCTIONAL PIN */ ++ { ++ *gpio_ctrl &= ~(1 << gpio_pin); ++ } ++ ++ spin_unlock_irqrestore(&closeLock, closeFlag); ++ ++ return (0); ++} ++ ++/**************************************************************************** ++ * FUNCTION: avalanche_gpio_out ++ ***************************************************************************/ ++int avalanche_gpio_out_bit(unsigned int gpio_pin, int value) ++{ ++ spinlock_t closeLock; ++ unsigned int closeFlag; ++ volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT; ++ ++ if(gpio_pin >= 32) ++ return(-1); ++ ++ spin_lock_irqsave(&closeLock, closeFlag); ++ if(value == TRUE) ++ *gpio_out |= 1 << gpio_pin; ++ else ++ *gpio_out &= ~(1 << gpio_pin); ++ spin_unlock_irqrestore(&closeLock, closeFlag); ++ ++ return(0); ++} ++ ++/**************************************************************************** ++ * FUNCTION: avalanche_gpio_in ++ ***************************************************************************/ ++int avalanche_gpio_in_bit(unsigned int gpio_pin) ++{ ++ spinlock_t closeLock; ++ unsigned int closeFlag; ++ volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN; ++ int ret_val = 0; ++ ++ if(gpio_pin >= 32) ++ return(-1); ++ ++ spin_lock_irqsave(&closeLock, closeFlag); ++ ret_val = ((*gpio_in) & (1 << gpio_pin)); ++ spin_unlock_irqrestore(&closeLock, closeFlag); ++ ++ return (ret_val); ++} ++ ++/**************************************************************************** ++ * FUNCTION: avalanche_gpio_out_val ++ ***************************************************************************/ ++int avalanche_gpio_out_value(unsigned int out_val, unsigned int out_mask, ++ unsigned int reg_index) ++{ ++ spinlock_t closeLock; ++ unsigned int closeFlag; ++ volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT; ++ ++ if(reg_index > 0) ++ return(-1); ++ ++ spin_lock_irqsave(&closeLock, closeFlag); ++ *gpio_out &= ~out_mask; ++ *gpio_out |= out_val; ++ spin_unlock_irqrestore(&closeLock, closeFlag); ++ ++ return(0); ++} ++ ++/**************************************************************************** ++ * FUNCTION: avalanche_gpio_in_value ++ ***************************************************************************/ ++int avalanche_gpio_in_value(unsigned int* in_val, unsigned int reg_index) ++{ ++ spinlock_t closeLock; ++ unsigned int closeFlag; ++ volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN; ++ ++ if(reg_index > 0) ++ return(-1); ++ ++ spin_lock_irqsave(&closeLock, closeFlag); ++ *in_val = *gpio_in; ++ spin_unlock_irqrestore(&closeLock, closeFlag); ++ ++ return (0); ++} ++ ++/*********************************************************************** ++ * ++ * Wakeup Control Module for TNETV1050 Communication Processor ++ * ++ ***********************************************************************/ ++ ++#define AVALANCHE_WAKEUP_POLARITY_BIT 16 ++ ++void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int, ++ AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl, ++ AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity) ++{ ++ volatile unsigned int *wakeup_status_reg = (unsigned int*) AVALANCHE_WAKEUP_CTRL_WKCR; ++ ++ /* enable/disable */ ++ if (wakeup_ctrl == WAKEUP_ENABLED) ++ /* enable wakeup */ ++ *wakeup_status_reg |= wakeup_int; ++ else ++ /* disable wakeup */ ++ *wakeup_status_reg &= (~wakeup_int); ++ ++ /* set polarity */ ++ if (wakeup_polarity == WAKEUP_ACTIVE_LOW) ++ *wakeup_status_reg |= (wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT); ++ else ++ *wakeup_status_reg &= ~(wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT); ++} ++ ++void avalanche_set_vbus_freq(unsigned int new_vbus_freq) ++{ ++ avalanche_vbus_freq = new_vbus_freq; ++} ++ ++unsigned int avalanche_get_vbus_freq() ++{ ++ return(avalanche_vbus_freq); ++} ++ ++unsigned int avalanche_get_chip_version_info() ++{ ++ return(*(volatile unsigned int*)AVALANCHE_CVR); ++} ++ ++SET_MDIX_ON_CHIP_FN_T p_set_mdix_on_chip_fn = NULL; ++ ++int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation) ++{ ++ if(p_set_mdix_on_chip_fn) ++ return (p_set_mdix_on_chip_fn(base_addr, operation)); ++ else ++ return(-1); ++} ++ ++unsigned int avalanche_is_mdix_on_chip(void) ++{ ++ return(p_set_mdix_on_chip_fn ? 1:0); ++} ++ ++EXPORT_SYMBOL(avalanche_reset_ctrl); ++EXPORT_SYMBOL(avalanche_get_reset_status); ++EXPORT_SYMBOL(avalanche_sys_reset); ++EXPORT_SYMBOL(avalanche_get_sys_last_reset_status); ++EXPORT_SYMBOL(avalanche_power_ctrl); ++EXPORT_SYMBOL(avalanche_get_power_status); ++EXPORT_SYMBOL(avalanche_set_global_power_mode); ++EXPORT_SYMBOL(avalanche_get_global_power_mode); ++EXPORT_SYMBOL(avalanche_set_mdix_on_chip); ++EXPORT_SYMBOL(avalanche_is_mdix_on_chip); ++ ++EXPORT_SYMBOL(avalanche_gpio_init); ++EXPORT_SYMBOL(avalanche_gpio_ctrl); ++EXPORT_SYMBOL(avalanche_gpio_out_bit); ++EXPORT_SYMBOL(avalanche_gpio_in_bit); ++EXPORT_SYMBOL(avalanche_gpio_out_value); ++EXPORT_SYMBOL(avalanche_gpio_in_value); ++ ++EXPORT_SYMBOL(avalanche_set_vbus_freq); ++EXPORT_SYMBOL(avalanche_get_vbus_freq); ++ ++EXPORT_SYMBOL(avalanche_get_chip_version_info); ++ +diff -urN kernel-base/arch/mips/ar7/ar7/paging.c kernel-current/arch/mips/ar7/ar7/paging.c +--- kernel-base/arch/mips/ar7/ar7/paging.c 1970-01-01 01:00:00.000000000 +0100 ++++ kernel-current/arch/mips/ar7/ar7/paging.c 2005-07-10 07:08:33.725758000 +0200 @@ -0,0 +1,314 @@ +/* + * -*- linux-c -*- @@ -389,26 +767,9 @@ diff -urN linux.old/arch/mips/ar7/avalanche/avalanche_paging.c linux.dev/arch/mi + + return; +} -diff -urN linux.old/arch/mips/ar7/avalanche/Makefile linux.dev/arch/mips/ar7/avalanche/Makefile ---- linux.old/arch/mips/ar7/avalanche/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/avalanche/Makefile 2005-07-07 04:39:14.417226000 +0200 -@@ -0,0 +1,13 @@ -+.S.s: -+ $(CPP) $(AFLAGS) $< -o $*.s -+ -+.S.o: -+ $(CC) $(AFLAGS) -c $< -o $*.o -+ -+EXTRA_CFLAGS := -DLITTLE_ENDIAN -D_LINK_KSEG0_ -+ -+O_TARGET := avalanche.o -+ -+obj-y += avalanche_paging.o avalanche_jump.o -+ -+include $(TOPDIR)/Rules.make -diff -urN linux.old/arch/mips/ar7/cmdline.c linux.dev/arch/mips/ar7/cmdline.c ---- linux.old/arch/mips/ar7/cmdline.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/cmdline.c 2005-07-07 04:39:14.419226000 +0200 +diff -urN kernel-base/arch/mips/ar7/cmdline.c kernel-current/arch/mips/ar7/cmdline.c +--- kernel-base/arch/mips/ar7/cmdline.c 1970-01-01 01:00:00.000000000 +0100 ++++ kernel-current/arch/mips/ar7/cmdline.c 2005-07-10 06:40:39.584266000 +0200 @@ -0,0 +1,64 @@ +/* + * Carsten Langgaard, carstenl@mips.com @@ -474,9 +835,9 @@ diff -urN linux.old/arch/mips/ar7/cmdline.c linux.dev/arch/mips/ar7/cmdline.c + --cp; + *cp = '\0'; +} -diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c ---- linux.old/arch/mips/ar7/init.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/init.c 2005-07-07 04:39:14.419226000 +0200 +diff -urN kernel-base/arch/mips/ar7/init.c kernel-current/arch/mips/ar7/init.c +--- kernel-base/arch/mips/ar7/init.c 1970-01-01 01:00:00.000000000 +0100 ++++ kernel-current/arch/mips/ar7/init.c 2005-07-10 17:53:38.565319696 +0200 @@ -0,0 +1,144 @@ +/* + * Carsten Langgaard, carstenl@mips.com @@ -501,6 +862,7 @@ diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c +#include +#include +#include ++#include + +#include +#include @@ -519,7 +881,6 @@ diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c +#define MAX_ENV_ENTRY 80 + +static t_env_var local_envp[MAX_ENV_ENTRY]; -+ +int init_debug = 0; + +char *prom_getenv(char *envname) @@ -622,10 +983,10 @@ diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c + + return 0; +} -diff -urN linux.old/arch/mips/ar7/irq.c linux.dev/arch/mips/ar7/irq.c ---- linux.old/arch/mips/ar7/irq.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/irq.c 2005-07-07 04:39:14.420226000 +0200 -@@ -0,0 +1,669 @@ +diff -urN kernel-base/arch/mips/ar7/irq.c kernel-current/arch/mips/ar7/irq.c +--- kernel-base/arch/mips/ar7/irq.c 1970-01-01 01:00:00.000000000 +0100 ++++ kernel-current/arch/mips/ar7/irq.c 2005-07-10 17:53:17.841470200 +0200 +@@ -0,0 +1,705 @@ +/* + * Nitin Dhingra, iamnd@ti.com + * Copyright (C) 2002 Texas Instruments, Inc. All rights reserved. @@ -1034,10 +1395,6 @@ diff -urN linux.old/arch/mips/ar7/irq.c linux.dev/arch/mips/ar7/irq.c + avalanche_hw0_ecregs->excr = 0xffffffff; /* clear secondary interrupts 0:31 */ + + -+ // avalanche_hw0_ipaceregs->ipacep = (2*get_avalanche_vbus_freq()/1000000)*4; -+ /* hack for speeding up the pacing. */ -+ printk("the pacing pre-scalar has been set as 600.\n"); -+ avalanche_hw0_ipaceregs->ipacep = 600; + /* Channel to line mapping, Line to Channel mapping */ + + for(i = 0; i < 40; i++) @@ -1295,10 +1652,67 @@ diff -urN linux.old/arch/mips/ar7/irq.c linux.dev/arch/mips/ar7/irq.c + +} + -diff -urN linux.old/arch/mips/ar7/Makefile linux.dev/arch/mips/ar7/Makefile ---- linux.old/arch/mips/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/Makefile 2005-07-07 04:39:14.417226000 +0200 -@@ -0,0 +1,12 @@ ++ ++#define AVALANCHE_MAX_PACING_BLK 3 ++#define AVALANCHE_PACING_LOW_VAL 2 ++#define AVALANCHE_PACING_HIGH_VAL 63 ++ ++int avalanche_request_pacing(int irq_nr, unsigned int blk_num, ++ unsigned int pace_value) ++{ ++ unsigned int blk_offset; ++ unsigned long flags; ++ ++ if(irq_nr < MIPS_EXCEPTION_OFFSET && ++ irq_nr >= AVALANCHE_INT_END_PRIMARY) ++ return (0); ++ ++ if(blk_num > AVALANCHE_MAX_PACING_BLK) ++ return(-1); ++ ++ if(pace_value > AVALANCHE_PACING_HIGH_VAL && ++ pace_value < AVALANCHE_PACING_LOW_VAL) ++ return(-1); ++ ++ blk_offset = blk_num*8; ++ ++ save_and_cli(flags); ++ ++ /* disable the interrupt pacing, if enabled previously */ ++ avalanche_hw0_ipaceregs->ipacemax &= ~(0xff << blk_offset); ++ ++ /* clear the pacing map */ ++ avalanche_hw0_ipaceregs->ipacemap &= ~(0xff << blk_offset); ++ ++ /* setup the new values */ ++ avalanche_hw0_ipaceregs->ipacemap |= ((AVINTNUM(irq_nr)) << blk_offset); ++ avalanche_hw0_ipaceregs->ipacemax |= ((0x80 | pace_value) << blk_offset); ++ ++ restore_flags(flags); ++ ++ return(0); ++} +diff -urN kernel-base/arch/mips/ar7/Makefile kernel-current/arch/mips/ar7/Makefile +--- kernel-base/arch/mips/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ kernel-current/arch/mips/ar7/Makefile 2005-07-10 17:53:46.635092904 +0200 +@@ -0,0 +1,28 @@ ++# $Id$ ++# Copyright (C) $Date$ $Author$ ++# ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 2 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ +.S.s: + $(CPP) $(AFLAGS) $< -o $*.s + @@ -1307,13 +1721,12 @@ diff -urN linux.old/arch/mips/ar7/Makefile linux.dev/arch/mips/ar7/Makefile + +O_TARGET := ar7.o + -+obj-y := tnetd73xx_misc.o -+obj-y += setup.o irq.o mipsIRQ.o reset.o init.o memory.o printf.o cmdline.o time.o ++obj-y := setup.o irq.o mipsIRQ.o reset.o init.o memory.o printf.o cmdline.o time.o + +include $(TOPDIR)/Rules.make -diff -urN linux.old/arch/mips/ar7/memory.c linux.dev/arch/mips/ar7/memory.c ---- linux.old/arch/mips/ar7/memory.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/memory.c 2005-07-07 04:39:14.420226000 +0200 +diff -urN kernel-base/arch/mips/ar7/memory.c kernel-current/arch/mips/ar7/memory.c +--- kernel-base/arch/mips/ar7/memory.c 1970-01-01 01:00:00.000000000 +0100 ++++ kernel-current/arch/mips/ar7/memory.c 2005-07-10 06:40:39.586266000 +0200 @@ -0,0 +1,130 @@ +/* + * Carsten Langgaard, carstenl@mips.com @@ -1379,15 +1792,15 @@ diff -urN linux.old/arch/mips/ar7/memory.c linux.dev/arch/mips/ar7/memory.c + + mdesc[0].type = yamon_dontuse; + mdesc[0].base = 0x00000000; -+ mdesc[0].size = AVALANCHE_SDRAM_BASE; ++ mdesc[0].size = CONFIG_AR7_MEMORY; + + mdesc[1].type = yamon_prom; -+ mdesc[1].base = AVALANCHE_SDRAM_BASE; ++ mdesc[1].base = CONFIG_AR7_MEMORY; + mdesc[1].size = 0x00020000; + + mdesc[2].type = yamon_free; -+ mdesc[2].base = AVALANCHE_SDRAM_BASE + 0x00020000; -+ mdesc[2].size = (memsize + AVALANCHE_SDRAM_BASE) - mdesc[2].base; ++ mdesc[2].base = CONFIG_AR7_MEMORY + 0x00020000; ++ mdesc[2].size = (memsize + CONFIG_AR7_MEMORY) - mdesc[2].base; + + return &mdesc[0]; +} @@ -1445,9 +1858,9 @@ diff -urN linux.old/arch/mips/ar7/memory.c linux.dev/arch/mips/ar7/memory.c + } + printk("Freeing prom memory: %ldkb freed\n", freed >> 10); +} -diff -urN linux.old/arch/mips/ar7/mipsIRQ.S linux.dev/arch/mips/ar7/mipsIRQ.S ---- linux.old/arch/mips/ar7/mipsIRQ.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/mipsIRQ.S 2005-07-07 04:39:14.421226000 +0200 +diff -urN kernel-base/arch/mips/ar7/mipsIRQ.S kernel-current/arch/mips/ar7/mipsIRQ.S +--- kernel-base/arch/mips/ar7/mipsIRQ.S 1970-01-01 01:00:00.000000000 +0100 ++++ kernel-current/arch/mips/ar7/mipsIRQ.S 2005-07-10 06:40:39.587266000 +0200 @@ -0,0 +1,120 @@ +/* + * Carsten Langgaard, carstenl@mips.com @@ -1569,10 +1982,10 @@ diff -urN linux.old/arch/mips/ar7/mipsIRQ.S linux.dev/arch/mips/ar7/mipsIRQ.S + j ret_from_irq + nop +END(mipsIRQ) -diff -urN linux.old/arch/mips/ar7/printf.c linux.dev/arch/mips/ar7/printf.c ---- linux.old/arch/mips/ar7/printf.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/printf.c 2005-07-07 04:39:14.421226000 +0200 -@@ -0,0 +1,51 @@ +diff -urN kernel-base/arch/mips/ar7/printf.c kernel-current/arch/mips/ar7/printf.c +--- kernel-base/arch/mips/ar7/printf.c 1970-01-01 01:00:00.000000000 +0100 ++++ kernel-current/arch/mips/ar7/printf.c 2005-07-10 06:40:39.587266000 +0200 +@@ -0,0 +1,54 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. @@ -1603,6 +2016,9 @@ diff -urN linux.old/arch/mips/ar7/printf.c linux.dev/arch/mips/ar7/printf.c +#include +#include + ++#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500)) ++#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */ ++ +static char ppbuf[1024]; + +void (*prom_print_str)(unsigned int out, char *s, int len); @@ -1624,9 +2040,9 @@ diff -urN linux.old/arch/mips/ar7/printf.c linux.dev/arch/mips/ar7/printf.c + return; + +} -diff -urN linux.old/arch/mips/ar7/reset.c linux.dev/arch/mips/ar7/reset.c ---- linux.old/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/reset.c 2005-07-07 04:39:14.421226000 +0200 +diff -urN kernel-base/arch/mips/ar7/reset.c kernel-current/arch/mips/ar7/reset.c +--- kernel-base/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100 ++++ kernel-current/arch/mips/ar7/reset.c 2005-07-10 06:40:39.587266000 +0200 @@ -0,0 +1,54 @@ +/* + * Carsten Langgaard, carstenl@mips.com @@ -1682,10 +2098,10 @@ diff -urN linux.old/arch/mips/ar7/reset.c linux.dev/arch/mips/ar7/reset.c + _machine_halt = ar7_machine_halt; + _machine_power_off = ar7_machine_power_off; +} -diff -urN linux.old/arch/mips/ar7/setup.c linux.dev/arch/mips/ar7/setup.c ---- linux.old/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/setup.c 2005-07-07 06:45:41.786771352 +0200 -@@ -0,0 +1,167 @@ +diff -urN kernel-base/arch/mips/ar7/setup.c kernel-current/arch/mips/ar7/setup.c +--- kernel-base/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100 ++++ kernel-current/arch/mips/ar7/setup.c 2005-07-10 06:40:39.588266000 +0200 +@@ -0,0 +1,120 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. @@ -1719,27 +2135,6 @@ diff -urN linux.old/arch/mips/ar7/setup.c linux.dev/arch/mips/ar7/setup.c +#include +#include + -+ -+#define _LINK_KSEG0_ -+#define LITTLE_ENDIAN -+#include -+#include -+ -+// Specific for ar7wrd -+unsigned int tnetd73xx_vbus_freq; -+#define BOOTCR_MIPS_ASYNC_MODE (1 << 25) -+#define AFECLK_FREQ 35328000 -+#define REFCLK_FREQ 25000000 -+#define OSC3_FREQ 24000000 -+#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000 -+ -+#if defined(CONFIG_AR7_MARVELL) -+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000 -+#else -+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2 -+#endif -+ -+ +#ifdef CONFIG_KGDB +extern void rs_kgdb_hook(int); +int remote_debug = 0; @@ -1752,30 +2147,6 @@ diff -urN linux.old/arch/mips/ar7/setup.c linux.dev/arch/mips/ar7/setup.c +extern void ar7_time_init(void); +extern void ar7_timer_setup(struct irqaction *irq); + -+/* maybe some of this is not needed? */ -+static void ar7_platform_init(void) -+{ -+ //tnetd73xx_gpio_init(); -+ -+ tnetd73xx_reset_ctrl(RESET_MODULE_UART0, OUT_OF_RESET); -+ //tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET); -+ //REG32_WRITE(TNETD73XX_GPIOENR, 0xf3fc3ff0); -+ -+ //tnetd73xx_reset_ctrl(RESET_MODULE_EPHY, IN_RESET); -+ //tnetd73xx_reset_ctrl(RESET_MODULE_EPHY, OUT_OF_RESET); -+ -+ tnetd73xx_clkc_init(AFECLK_FREQ, REFCLK_FREQ, OSC3_FREQ); -+ -+ tnetd73xx_vbus_freq = tnetd73xx_clkc_get_freq(CLKC_SYS) / 2; -+ -+#if defined(CONFIG_AR7WRD) -+ if(! (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE)) { -+ tnetd73xx_clkc_set_freq(CLKC_MIPS, CLK_MHZ(150)); -+ } -+#endif -+ -+} -+ +const char *get_system_type(void) +{ + return "Texas Instruments AR7"; @@ -1846,16 +2217,14 @@ diff -urN linux.old/arch/mips/ar7/setup.c linux.dev/arch/mips/ar7/setup.c + + rtc_ops = &no_rtc_ops; + -+ ar7_platform_init(); -+ + ar7_reboot_setup(); + + board_time_init = ar7_time_init; + board_timer_setup = ar7_timer_setup; +} -diff -urN linux.old/arch/mips/ar7/time.c linux.dev/arch/mips/ar7/time.c ---- linux.old/arch/mips/ar7/time.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/time.c 2005-07-07 04:39:14.422226000 +0200 +diff -urN kernel-base/arch/mips/ar7/time.c kernel-current/arch/mips/ar7/time.c +--- kernel-base/arch/mips/ar7/time.c 1970-01-01 01:00:00.000000000 +0100 ++++ kernel-current/arch/mips/ar7/time.c 2005-07-10 06:40:39.588266000 +0200 @@ -0,0 +1,125 @@ +/* + * Carsten Langgaard, carstenl@mips.com @@ -1950,7 +2319,7 @@ diff -urN linux.old/arch/mips/ar7/time.c linux.dev/arch/mips/ar7/time.c + */ +static unsigned long __init cal_r4koff(void) +{ -+ return ((CONFIG_AR7_FREQUENCY*500000)/HZ); ++ return ((CONFIG_AR7_CPU_FREQUENCY*500000)/HZ); +} + +void __init ar7_time_init(void) @@ -1982,938 +2351,10 @@ diff -urN linux.old/arch/mips/ar7/time.c linux.dev/arch/mips/ar7/time.c + write_c0_compare(r4k_cur); + set_c0_status(ALLINTS); +} -diff -urN linux.old/arch/mips/ar7/tnetd73xx_misc.c linux.dev/arch/mips/ar7/tnetd73xx_misc.c ---- linux.old/arch/mips/ar7/tnetd73xx_misc.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/tnetd73xx_misc.c 2005-07-07 04:39:14.423225000 +0200 -@@ -0,0 +1,924 @@ -+/****************************************************************************** -+ * FILE PURPOSE: TNETD73xx Misc modules API Source -+ ****************************************************************************** -+ * FILE NAME: tnetd73xx_misc.c -+ * -+ * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO -+ * FSER Modules API -+ * As per TNETD73xx specifications -+ * -+ * REVISION HISTORY: -+ * 27 Nov 02 - Sharath Kumar PSP TII -+ * 14 Feb 03 - Anant Gole PSP TII -+ * -+ * (C) Copyright 2002, Texas Instruments, Inc -+ *******************************************************************************/ -+ -+#define LITTLE_ENDIAN -+#define _LINK_KSEG0_ -+ -+#include -+#include -+#include -+ -+/* TNETD73XX Revision */ -+u32 tnetd73xx_get_revision(void) -+{ -+ /* Read Chip revision register - This register is from GPIO module */ -+ return ( (u32) REG32_DATA(TNETD73XX_CVR)); -+} -+ -+/***************************************************************************** -+ * Reset Control Module -+ *****************************************************************************/ -+ -+ -+void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, TNETD73XX_RESET_CTRL_T reset_ctrl) -+{ -+ u32 reset_status; -+ -+ /* read current reset register */ -+ REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status); -+ -+ if (reset_ctrl == OUT_OF_RESET) -+ { -+ /* bring module out of reset */ -+ reset_status |= (1 << reset_module); -+ } -+ else -+ { -+ /* put module in reset */ -+ reset_status &= (~(1 << reset_module)); -+ } -+ -+ /* write to the reset register */ -+ REG32_WRITE(TNETD73XX_RST_CTRL_PRCR, reset_status); -+} -+ -+ -+TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status (TNETD73XX_RESET_MODULE_T reset_module) -+{ -+ u32 reset_status; -+ -+ REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status); -+ return ( (reset_status & (1 << reset_module)) ? OUT_OF_RESET : IN_RESET ); -+} -+ -+void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode) -+{ -+ REG32_WRITE(TNETD73XX_RST_CTRL_SWRCR, mode); -+} -+ -+#define TNETD73XX_RST_CTRL_RSR_MASK 0x3 -+ -+TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status() -+{ -+ u32 sys_reset_status; -+ -+ REG32_READ(TNETD73XX_RST_CTRL_RSR, sys_reset_status); -+ -+ return ( (TNETD73XX_SYS_RESET_STATUS_T) (sys_reset_status & TNETD73XX_RST_CTRL_RSR_MASK) ); -+} -+ -+ -+/***************************************************************************** -+ * Power Control Module -+ *****************************************************************************/ -+#define TNETD73XX_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */ -+#define TNETD73XX_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */ -+ -+ -+void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl) -+{ -+ u32 power_status; -+ -+ /* read current power down control register */ -+ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status); -+ -+ if (power_ctrl == POWER_CTRL_POWER_DOWN) -+ { -+ /* power down the module */ -+ power_status |= (1 << power_module); -+ } -+ else -+ { -+ /* power on the module */ -+ power_status &= (~(1 << power_module)); -+ } -+ -+ /* write to the reset register */ -+ REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status); -+} -+ -+TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module) -+{ -+ u32 power_status; -+ -+ /* read current power down control register */ -+ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status); -+ -+ return ( (power_status & (1 << power_module)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP ); -+} -+ -+void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode) -+{ -+ u32 power_status; -+ -+ /* read current power down control register */ -+ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status); -+ -+ power_status &= TNETD73XX_GLOBAL_POWER_DOWN_MASK; -+ power_status |= ( power_mode << TNETD73XX_GLOBAL_POWER_DOWN_BIT); -+ -+ /* write to power down control register */ -+ REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status); -+} -+ -+TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode() -+{ -+ u32 power_status; -+ -+ /* read current power down control register */ -+ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status); -+ -+ power_status &= (~TNETD73XX_GLOBAL_POWER_DOWN_MASK); -+ power_status = ( power_status >> TNETD73XX_GLOBAL_POWER_DOWN_BIT); -+ -+ return ( (TNETD73XX_SYS_POWER_MODE_T) power_status ); -+} -+ -+ -+/***************************************************************************** -+ * Wakeup Control -+ *****************************************************************************/ -+ -+#define TNETD73XX_WAKEUP_POLARITY_BIT 16 -+ -+void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int, -+ TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl, -+ TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity) -+{ -+ u32 wakeup_status; -+ -+ /* read the wakeup control register */ -+ REG32_READ(TNETD73XX_POWER_CTRL_WKCR, wakeup_status); -+ -+ /* enable/disable */ -+ if (wakeup_ctrl == WAKEUP_ENABLED) -+ { -+ /* enable wakeup */ -+ wakeup_status |= wakeup_int; -+ } -+ else -+ { -+ /* disable wakeup */ -+ wakeup_status &= (~wakeup_int); -+ } -+ -+ /* set polarity */ -+ if (wakeup_polarity == WAKEUP_ACTIVE_LOW) -+ { -+ wakeup_status |= (wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT); -+ } -+ else -+ { -+ wakeup_status &= ~(wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT); -+ } -+ -+ /* write the wakeup control register */ -+ REG32_WRITE(TNETD73XX_POWER_CTRL_WKCR, wakeup_status); -+} -+ -+ -+/***************************************************************************** -+ * FSER Control -+ *****************************************************************************/ -+ -+void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode) -+{ -+ REG32_WRITE(TNETD73XX_FSER_BASE, fser_mode); -+} -+ -+/***************************************************************************** -+ * Clock Control -+ *****************************************************************************/ -+ -+#define MIN(x,y) ( ((x) < (y)) ? (x) : (y) ) -+#define MAX(x,y) ( ((x) > (y)) ? (x) : (y) ) -+#define ABS(x) ( ((signed)(x) > 0) ? (x) : (-(x)) ) -+#define CEIL(x,y) ( ((x) + (y) / 2) / (y) ) -+ -+#define CLKC_CLKCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x20 + (0x20 * (x))) -+#define CLKC_CLKPLLCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x30 + (0x20 * (x))) -+ -+#define CLKC_PRE_DIVIDER 0x0000001F -+#define CLKC_POST_DIVIDER 0x001F0000 -+ -+#define CLKC_PLL_STATUS 0x1 -+#define CLKC_PLL_FACTOR 0x0000F000 -+ -+#define BOOTCR_PLL_BYPASS (1 << 5) -+#define BOOTCR_MIPS_ASYNC_MODE (1 << 25) -+ -+#define MIPS_PLL_SELECT 0x00030000 -+#define SYSTEM_PLL_SELECT 0x0000C000 -+#define USB_PLL_SELECT 0x000C0000 -+#define ADSLSS_PLL_SELECT 0x00C00000 -+ -+#define MIPS_AFECLKI_SELECT 0x00000000 -+#define MIPS_REFCLKI_SELECT 0x00010000 -+#define MIPS_XTAL3IN_SELECT 0x00020000 -+ -+#define SYSTEM_AFECLKI_SELECT 0x00000000 -+#define SYSTEM_REFCLKI_SELECT 0x00004000 -+#define SYSTEM_XTAL3IN_SELECT 0x00008000 -+#define SYSTEM_MIPSPLL_SELECT 0x0000C000 -+ -+#define USB_SYSPLL_SELECT 0x00000000 -+#define USB_REFCLKI_SELECT 0x00040000 -+#define USB_XTAL3IN_SELECT 0x00080000 -+#define USB_MIPSPLL_SELECT 0x000C0000 -+ -+#define ADSLSS_AFECLKI_SELECT 0x00000000 -+#define ADSLSS_REFCLKI_SELECT 0x00400000 -+#define ADSLSS_XTAL3IN_SELECT 0x00800000 -+#define ADSLSS_MIPSPLL_SELECT 0x00C00000 -+ -+#define SYS_MAX CLK_MHZ(150) -+#define SYS_MIN CLK_MHZ(1) -+ -+#define MIPS_SYNC_MAX SYS_MAX -+#define MIPS_ASYNC_MAX CLK_MHZ(160) -+#define MIPS_MIN CLK_MHZ(1) -+ -+#define USB_MAX CLK_MHZ(100) -+#define USB_MIN CLK_MHZ(1) -+ -+#define ADSL_MAX CLK_MHZ(180) -+#define ADSL_MIN CLK_MHZ(1) -+ -+#define PLL_MUL_MAXFACTOR 15 -+#define MAX_DIV_VALUE 32 -+#define MIN_DIV_VALUE 1 -+ -+#define MIN_PLL_INP_FREQ CLK_MHZ(8) -+#define MAX_PLL_INP_FREQ CLK_MHZ(100) -+ -+#define DIVIDER_LOCK_TIME 10100 -+#define PLL_LOCK_TIME 10100 * 75 -+ -+ -+ -+ /**************************************************************************** -+ * DATA PURPOSE: PRIVATE Variables -+ **************************************************************************/ -+ static u32 *clk_src[4]; -+ static u32 mips_pll_out; -+ static u32 sys_pll_out; -+ static u32 afeclk_inp; -+ static u32 refclk_inp; -+ static u32 xtal_inp; -+ static u32 present_min; -+ static u32 present_max; -+ -+ /* Forward References */ -+ static u32 find_gcd(u32 min, u32 max); -+ static u32 compute_prediv( u32 divider, u32 min, u32 max); -+ static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider); -+ static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id); -+ static void find_approx(u32 *,u32 *,u32); -+ -+ /**************************************************************************** -+ * FUNCTION: tnetd73xx_clkc_init -+ **************************************************************************** -+ * Description: The routine initializes the internal variables depending on -+ * on the sources selected for different clocks. -+ ***************************************************************************/ -+void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in) -+{ -+ -+ u32 choice; -+ -+ afeclk_inp = afeclk; -+ refclk_inp = refclk; -+ xtal_inp = xtal3in; -+ -+ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & MIPS_PLL_SELECT; -+ switch(choice) -+ { -+ case MIPS_AFECLKI_SELECT: -+ clk_src[CLKC_MIPS] = &afeclk_inp; -+ break; -+ -+ case MIPS_REFCLKI_SELECT: -+ clk_src[CLKC_MIPS] = &refclk_inp; -+ break; -+ -+ case MIPS_XTAL3IN_SELECT: -+ clk_src[CLKC_MIPS] = &xtal_inp; -+ break; -+ -+ default : -+ clk_src[CLKC_MIPS] = 0; -+ -+ } -+ -+ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & SYSTEM_PLL_SELECT; -+ switch(choice) -+ { -+ case SYSTEM_AFECLKI_SELECT: -+ clk_src[CLKC_SYS] = &afeclk_inp; -+ break; -+ -+ case SYSTEM_REFCLKI_SELECT: -+ clk_src[CLKC_SYS] = &refclk_inp; -+ break; -+ -+ case SYSTEM_XTAL3IN_SELECT: -+ clk_src[CLKC_SYS] = &xtal_inp; -+ break; -+ -+ case SYSTEM_MIPSPLL_SELECT: -+ clk_src[CLKC_SYS] = &mips_pll_out; -+ break; -+ -+ default : -+ clk_src[CLKC_SYS] = 0; -+ -+ } -+ -+ -+ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & ADSLSS_PLL_SELECT; -+ switch(choice) -+ { -+ case ADSLSS_AFECLKI_SELECT: -+ clk_src[CLKC_ADSLSS] = &afeclk_inp; -+ break; -+ -+ case ADSLSS_REFCLKI_SELECT: -+ clk_src[CLKC_ADSLSS] = &refclk_inp; -+ break; -+ -+ case ADSLSS_XTAL3IN_SELECT: -+ clk_src[CLKC_ADSLSS] = &xtal_inp; -+ break; -+ -+ case ADSLSS_MIPSPLL_SELECT: -+ clk_src[CLKC_ADSLSS] = &mips_pll_out; -+ break; -+ -+ default : -+ clk_src[CLKC_ADSLSS] = 0; -+ -+ } -+ -+ -+ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & USB_PLL_SELECT; -+ switch(choice) -+ { -+ case USB_SYSPLL_SELECT: -+ clk_src[CLKC_USB] = &sys_pll_out ; -+ break; -+ -+ case USB_REFCLKI_SELECT: -+ clk_src[CLKC_USB] = &refclk_inp; -+ break; -+ -+ case USB_XTAL3IN_SELECT: -+ clk_src[CLKC_USB] = &xtal_inp; -+ break; -+ -+ case USB_MIPSPLL_SELECT: -+ clk_src[CLKC_USB] = &mips_pll_out; -+ break; -+ -+ default : -+ clk_src[CLKC_USB] = 0; -+ -+ } -+} -+ -+ -+ -+/**************************************************************************** -+ * FUNCTION: tnetd73xx_clkc_set_freq -+ **************************************************************************** -+ * Description: The above routine is called to set the output_frequency of the -+ * selected clock(using clk_id) to the required value given -+ * by the variable output_freq. -+ ***************************************************************************/ -+TNETD73XX_ERR tnetd73xx_clkc_set_freq -+( -+ TNETD73XX_CLKC_ID_T clk_id, -+ u32 output_freq -+ ) -+{ -+ u32 base_freq; -+ u32 multiplier; -+ u32 divider; -+ u32 min_prediv; -+ u32 max_prediv; -+ u32 prediv; -+ u32 postdiv; -+ u32 temp; -+ -+ /* check if PLLs are bypassed*/ -+ if(REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS) -+ { -+ return TNETD73XX_ERR_ERROR; -+ } -+ -+ /*check if the requested output_frequency is in valid range*/ -+ switch( clk_id ) -+ { -+ case CLKC_SYS: -+ if( output_freq < SYS_MIN || output_freq > SYS_MAX) -+ { -+ return TNETD73XX_ERR_ERROR; -+ } -+ present_min = SYS_MIN; -+ present_max = SYS_MAX; -+ break; -+ -+ case CLKC_MIPS: -+ if((output_freq < MIPS_MIN) || -+ (output_freq > ((REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX))) -+ { -+ return TNETD73XX_ERR_ERROR; -+ } -+ present_min = MIPS_MIN; -+ present_max = (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX; -+ break; -+ -+ case CLKC_USB: -+ if( output_freq < USB_MIN || output_freq > USB_MAX) -+ { -+ return TNETD73XX_ERR_ERROR; -+ } -+ present_min = USB_MIN; -+ present_max = USB_MAX; -+ break; -+ -+ case CLKC_ADSLSS: -+ if( output_freq < ADSL_MIN || output_freq > ADSL_MAX) -+ { -+ return TNETD73XX_ERR_ERROR; -+ } -+ present_min = ADSL_MIN; -+ present_max = ADSL_MAX; -+ break; -+ } -+ -+ -+ base_freq = get_base_frequency(clk_id); -+ -+ -+ /* check for minimum base frequency value */ -+ if( base_freq < MIN_PLL_INP_FREQ) -+ { -+ return TNETD73XX_ERR_ERROR; -+ } -+ -+ get_val(output_freq, base_freq, &multiplier, ÷r); -+ -+ /* check multiplier range */ -+ if( (multiplier > PLL_MUL_MAXFACTOR) || (multiplier <= 0) ) -+ { -+ return TNETD73XX_ERR_ERROR; -+ } -+ -+ /* check divider value */ -+ if( divider == 0 ) -+ { -+ return TNETD73XX_ERR_ERROR; -+ } -+ -+ /*compute minimum and maximum predivider values */ -+ min_prediv = MAX(base_freq / MAX_PLL_INP_FREQ + 1, divider / MAX_DIV_VALUE + 1); -+ max_prediv = MIN(base_freq / MIN_PLL_INP_FREQ, MAX_DIV_VALUE); -+ -+ /*adjust the value of divider so that it not less than minimum predivider value*/ -+ if (divider < min_prediv) -+ { -+ temp = CEIL(min_prediv, divider); -+ if ((temp * multiplier) > PLL_MUL_MAXFACTOR) -+ { -+ return TNETD73XX_ERR_ERROR ; -+ } -+ else -+ { -+ multiplier = temp * multiplier; -+ divider = min_prediv; -+ } -+ -+ } -+ -+ /* compute predivider and postdivider values */ -+ prediv = compute_prediv (divider, min_prediv, max_prediv); -+ postdiv = CEIL(divider,prediv); -+ -+ /*return fail if postdivider value falls out of range */ -+ if(postdiv > MAX_DIV_VALUE) -+ { -+ return TNETD73XX_ERR_ERROR; -+ } -+ -+ -+ /*write predivider and postdivider values*/ -+ /* pre-Divider and post-divider are 5 bit N+1 dividers */ -+ REG32_WRITE(CLKC_CLKCR(clk_id), ((postdiv -1) & 0x1F) << 16 | ((prediv -1) & 0x1F) ); -+ -+ /*wait for divider output to stabilise*/ -+ for(temp =0; temp < DIVIDER_LOCK_TIME; temp++); -+ -+ /*write to PLL clock register*/ -+ -+ if(clk_id == CLKC_SYS) -+ { -+ /* but before writing put DRAM to hold mode */ -+ REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) |= 0x80000000; -+ } -+ /*Bring PLL into div mode */ -+ REG32_WRITE(CLKC_CLKPLLCR(clk_id), 0x4); -+ -+ /*compute the word to be written to PLLCR -+ *corresponding to multiplier value -+ */ -+ multiplier = (((multiplier - 1) & 0xf) << 12)| ((255 <<3) | 0x0e); -+ -+ /* wait till PLL enters div mode */ -+ while(REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS) -+ /*nothing*/; -+ -+ REG32_WRITE(CLKC_CLKPLLCR(clk_id), multiplier); -+ -+ while(!REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS) -+ /*nothing*/; -+ -+ -+ /*wait for External pll to lock*/ -+ for(temp =0; temp < PLL_LOCK_TIME; temp++); -+ -+ if(clk_id == CLKC_SYS) -+ { -+ /* Bring DRAM out of hold */ -+ REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) &= ~0x80000000; -+ } -+ -+ return TNETD73XX_ERR_OK ; -+} -+ -+/**************************************************************************** -+ * FUNCTION: tnetd73xx_clkc_get_freq -+ **************************************************************************** -+ * Description: The above routine is called to get the output_frequency of the -+ * selected clock( clk_id) -+ ***************************************************************************/ -+u32 tnetd73xx_clkc_get_freq -+( -+ TNETD73XX_CLKC_ID_T clk_id -+ ) -+{ -+ -+ u32 clk_ctrl_register; -+ u32 clk_pll_setting; -+ u32 clk_predivider; -+ u32 clk_postdivider; -+ u16 pll_factor; -+ u32 base_freq; -+ u32 divider; -+ -+ base_freq = get_base_frequency(clk_id); -+ -+ clk_ctrl_register = REG32_DATA(CLKC_CLKCR(clk_id)); -+ -+ /* pre-Divider and post-divider are 5 bit N+1 dividers */ -+ clk_predivider = (CLKC_PRE_DIVIDER & clk_ctrl_register) + 1; -+ clk_postdivider = ((CLKC_POST_DIVIDER & clk_ctrl_register) >> 16) + 1; -+ -+ divider = clk_predivider * clk_postdivider; -+ -+ -+ if( (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS)) -+ { -+ return (CEIL(base_freq, divider)); /* PLLs bypassed.*/ -+ } -+ -+ -+ else -+ { -+ /* return the current clock speed based upon the PLL setting */ -+ clk_pll_setting = REG32_DATA(CLKC_CLKPLLCR(clk_id)); -+ -+ /* Get the PLL multiplication factor */ -+ pll_factor = ((clk_pll_setting & CLKC_PLL_FACTOR) >> 12) + 1; -+ -+ /* Check if we're in divide mode or multiply mode */ -+ if((clk_pll_setting & 0x1) == 0) -+ { -+ /* We're in divide mode */ -+ if(pll_factor < 0x10) -+ return (CEIL(base_freq >> 1, divider)); -+ else -+ return (CEIL(base_freq >> 2, divider)); -+ } -+ -+ else /* We're in PLL mode */ -+ { -+ /* See if PLLNDIV & PLLDIV are set */ -+ if((clk_pll_setting & 0x0800) && (clk_pll_setting & 0x2)) -+ { -+ if(clk_pll_setting & 0x1000) -+ { -+ /* clk = base_freq * k/2 */ -+ return(CEIL((base_freq * pll_factor) >> 1, divider)); -+ } -+ else -+ { -+ /* clk = base_freq * (k-1) / 4)*/ -+ return(CEIL((base_freq * (pll_factor - 1)) >>2, divider)); -+ } -+ } -+ else -+ { -+ if(pll_factor < 0x10) -+ { -+ /* clk = base_freq * k */ -+ return(CEIL(base_freq * pll_factor, divider)); -+ } -+ -+ else -+ { -+ /* clk = base_freq */ -+ return(CEIL(base_freq, divider)); -+ } -+ } -+ } -+ return(0); /* Should never reach here */ -+ -+ } -+ -+} -+ -+ -+/* local helper functions */ -+ -+/**************************************************************************** -+ * FUNCTION: get_base_frequency -+ **************************************************************************** -+ * Description: The above routine is called to get base frequency of the clocks. -+ ***************************************************************************/ -+ -+static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id) -+{ -+ /* update the current MIPs PLL output value, if the required -+ * source is MIPS PLL -+ */ -+ if ( clk_src[clk_id] == &mips_pll_out) -+ { -+ *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_MIPS); -+ } -+ -+ -+ /* update the current System PLL output value, if the required -+ * source is system PLL -+ */ -+ if ( clk_src[clk_id] == &sys_pll_out) -+ { -+ *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_SYS); -+ } -+ -+ return (*clk_src[clk_id]); -+ -+} -+ -+ -+ -+/**************************************************************************** -+ * FUNCTION: find_gcd -+ **************************************************************************** -+ * Description: The above routine is called to find gcd of 2 numbers. -+ ***************************************************************************/ -+static u32 find_gcd -+( -+ u32 min, -+ u32 max -+ ) -+{ -+ if (max % min == 0) -+ { -+ return min; -+ } -+ else -+ { -+ return find_gcd(max % min, min); -+ } -+} -+ -+/**************************************************************************** -+ * FUNCTION: compute_prediv -+ **************************************************************************** -+ * Description: The above routine is called to compute predivider value -+ ***************************************************************************/ -+static u32 compute_prediv(u32 divider, u32 min, u32 max) -+{ -+ u16 prediv; -+ -+ /* return the divider itself it it falls within the range of predivider*/ -+ if (min <= divider && divider <= max) -+ { -+ return divider; -+ } -+ -+ /* find a value for prediv such that it is a factor of divider */ -+ for (prediv = max; prediv >= min ; prediv--) -+ { -+ if ( (divider % prediv) == 0 ) -+ { -+ return prediv; -+ } -+ } -+ -+ /* No such factor exists, return min as prediv */ -+ return min; -+} -+ -+/**************************************************************************** -+ * FUNCTION: get_val -+ **************************************************************************** -+ * Description: This routine is called to get values of divider and multiplier. -+ ***************************************************************************/ -+ -+static void get_val(u32 output_freq, u32 base_freq,u32 *multiplier, u32 *divider) -+{ -+ u32 temp_mul; -+ u32 temp_div; -+ u32 gcd; -+ u32 min_freq; -+ u32 max_freq; -+ -+ /* find gcd of base_freq, output_freq */ -+ min_freq = (base_freq < output_freq) ? base_freq : output_freq; -+ max_freq = (base_freq > output_freq) ? base_freq : output_freq; -+ gcd = find_gcd(min_freq , max_freq); -+ -+ if(gcd == 0) -+ return; /* ERROR */ -+ -+ /* compute values of multiplier and divider */ -+ temp_mul = output_freq / gcd; -+ temp_div = base_freq / gcd; -+ -+ -+ /* set multiplier such that 1 <= multiplier <= PLL_MUL_MAXFACTOR */ -+ if( temp_mul > PLL_MUL_MAXFACTOR ) -+ { -+ if((temp_mul / temp_div) > PLL_MUL_MAXFACTOR) -+ return; -+ -+ find_approx(&temp_mul,&temp_div,base_freq); -+ } -+ -+ *multiplier = temp_mul; -+ *divider = temp_div; -+} -+ -+/**************************************************************************** -+ * FUNCTION: find_approx -+ **************************************************************************** -+ * Description: This function gets the approx value of num/denom. -+ ***************************************************************************/ -+ -+static void find_approx(u32 *num,u32 *denom,u32 base_freq) -+{ -+ u32 num1; -+ u32 denom1; -+ u32 num2; -+ u32 denom2; -+ int32_t closest; -+ int32_t prev_closest; -+ u32 temp_num; -+ u32 temp_denom; -+ u32 normalize; -+ u32 gcd; -+ u32 output_freq; -+ -+ num1 = *num; -+ denom1 = *denom; -+ -+ prev_closest = 0x7fffffff; /* maximum possible value */ -+ num2 = num1; -+ denom2 = denom1; -+ -+ /* start with max */ -+ for(temp_num = 15; temp_num >=1; temp_num--) -+ { -+ -+ temp_denom = CEIL(temp_num * denom1, num1); -+ output_freq = (temp_num * base_freq) / temp_denom; -+ -+ if(temp_denom < 1) -+ { -+ break; -+ } -+ else -+ { -+ normalize = CEIL(num1,temp_num); -+ closest = (ABS((num1 * (temp_denom) ) - (temp_num * denom1))) * normalize; -+ if(closest < prev_closest && output_freq > present_min && output_freq #include @@ -3160,584 +2627,295 @@ diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, 0x80); else if (cpu_has_4kex) memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80); - else - memcpy((void *)(KSEG0 + 0x080), &except_vec3_generic, 0x80); -+#endif - - if (current_cpu_data.cputype == CPU_R6000 || - current_cpu_data.cputype == CPU_R6000A) { -@@ -1023,7 +1074,11 @@ - if (board_nmi_handler_setup) - board_nmi_handler_setup(); - -+#ifdef CONFIG_AR7 -+ flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x200); -+#else - flush_icache_range(KSEG0, KSEG0 + 0x400); -+#endif - - per_cpu_trap_init(); - } -diff -urN linux.old/arch/mips/lib/promlib.c linux.dev/arch/mips/lib/promlib.c ---- linux.old/arch/mips/lib/promlib.c 2005-07-07 05:38:31.345491560 +0200 -+++ linux.dev/arch/mips/lib/promlib.c 2005-07-07 04:39:14.426225000 +0200 -@@ -1,3 +1,4 @@ -+#ifndef CONFIG_AR7 - #include - #include - -@@ -22,3 +23,4 @@ - } - va_end(args); - } -+#endif -diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile ---- linux.old/arch/mips/Makefile 2005-07-07 05:38:31.320495360 +0200 -+++ linux.dev/arch/mips/Makefile 2005-07-07 04:39:14.510212000 +0200 -@@ -369,6 +369,16 @@ - endif - - # -+# Texas Instruments AR7 -+# -+ -+ifdef CONFIG_AR7 -+LIBS += arch/mips/ar7/ar7.o arch/mips/ar7/avalanche/avalanche.o -+SUBDIRS += arch/mips/ar7 arch/mips/ar7/avalanche -+LOADADDR += 0x94020000 -+endif -+ -+# - # DECstation family - # - ifdef CONFIG_DECSTATION -diff -urN linux.old/arch/mips/mm/init.c linux.dev/arch/mips/mm/init.c ---- linux.old/arch/mips/mm/init.c 2005-07-07 05:38:31.345491560 +0200 -+++ linux.dev/arch/mips/mm/init.c 2005-07-07 04:39:14.426225000 +0200 -@@ -40,8 +40,10 @@ - - mmu_gather_t mmu_gathers[NR_CPUS]; - unsigned long highstart_pfn, highend_pfn; -+#ifndef CONFIG_AR7_PAGING - static unsigned long totalram_pages; - static unsigned long totalhigh_pages; -+#endif - - void pgd_init(unsigned long page) - { -@@ -235,6 +237,7 @@ - #endif - } - -+#ifndef CONFIG_AR7_PAGING - void __init paging_init(void) - { - unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0}; -@@ -272,6 +275,7 @@ - - free_area_init(zones_size); - } -+#endif - - #define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT) - #define PFN_DOWN(x) ((x) >> PAGE_SHIFT) -@@ -298,6 +302,7 @@ - return 0; - } - -+#ifndef CONFIG_AR7_PAGING - void __init mem_init(void) - { - unsigned long codesize, reservedpages, datasize, initsize; -@@ -359,6 +364,7 @@ - initsize >> 10, - (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10))); - } -+#endif - - #ifdef CONFIG_BLK_DEV_INITRD - void free_initrd_mem(unsigned long start, unsigned long end) -@@ -376,6 +382,7 @@ - } - #endif - -+#ifndef CONFIG_AR7_PAGING - extern char __init_begin, __init_end; - extern void prom_free_prom_memory(void) __init; - -@@ -383,7 +390,9 @@ - { - unsigned long addr; - -+#ifndef CONFIG_AR7 - prom_free_prom_memory (); -+#endif - - addr = (unsigned long) &__init_begin; - while (addr < (unsigned long) &__init_end) { -@@ -409,3 +418,4 @@ - - return; - } -+#endif -diff -urN linux.old/arch/mips/mm/tlb-r4k.c linux.dev/arch/mips/mm/tlb-r4k.c ---- linux.old/arch/mips/mm/tlb-r4k.c 2005-07-07 05:38:31.346491408 +0200 -+++ linux.dev/arch/mips/mm/tlb-r4k.c 2005-07-07 04:39:14.427225000 +0200 -@@ -20,6 +20,10 @@ - #include - #include - -+#ifdef CONFIG_AR7 -+#include -+#endif -+ - extern char except_vec0_nevada, except_vec0_r4000, except_vec0_r4600; - - /* CP0 hazard avoidance. */ -@@ -375,7 +379,12 @@ - else if (current_cpu_data.cputype == CPU_R4600) - memcpy((void *)KSEG0, &except_vec0_r4600, 0x80); - else -+#ifdef CONFIG_AR7 -+ memcpy((void *)AVALANCHE_VECS_KSEG0, &except_vec0_r4000, 0x80); -+ flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x80); -+#else - memcpy((void *)KSEG0, &except_vec0_r4000, 0x80); - flush_icache_range(KSEG0, KSEG0 + 0x80); -+#endif - } - } -diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c ---- linux.old/drivers/char/serial.c 2005-07-07 05:38:31.348491104 +0200 -+++ linux.dev/drivers/char/serial.c 2005-07-07 04:39:14.429225000 +0200 -@@ -419,7 +419,40 @@ - return 0; - } - --#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD) -+#if defined(CONFIG_AR7) -+ -+static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset) -+{ -+ return (inb(info->port + (offset * 4)) & 0xff); -+} -+ -+ -+static _INLINE_ unsigned int serial_inp(struct async_struct *info, int offset) -+{ -+#ifdef CONFIG_SERIAL_NOPAUSE_IO -+ return (inb(info->port + (offset * 4)) & 0xff); -+#else -+ return (inb_p(info->port + (offset * 4)) & 0xff); -+#endif -+} -+ -+static _INLINE_ void serial_out(struct async_struct *info, int offset, int value) -+{ -+ outb(value, info->port + (offset * 4)); -+} -+ -+ -+static _INLINE_ void serial_outp(struct async_struct *info, int offset, -+ int value) -+{ -+#ifdef CONFIG_SERIAL_NOPAUSE_IO -+ outb(value, info->port + (offset * 4)); -+#else -+ outb_p(value, info->port + (offset * 4)); -+#endif -+} -+ -+#elif defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD) - - #include - -@@ -478,8 +511,10 @@ - * needed for certain old 386 machines, I've left these #define's - * in.... - */ -+#ifdef CONFIG_AR7 - #define serial_inp(info, offset) serial_in(info, offset) - #define serial_outp(info, offset, value) serial_out(info, offset, value) + else + memcpy((void *)(KSEG0 + 0x080), &except_vec3_generic, 0x80); +#endif + if (current_cpu_data.cputype == CPU_R6000 || + current_cpu_data.cputype == CPU_R6000A) { +@@ -1023,7 +1074,11 @@ + if (board_nmi_handler_setup) + board_nmi_handler_setup(); - /* -@@ -1728,7 +1763,15 @@ - /* Special case since 134 is really 134.5 */ - quot = (2*baud_base / 269); - else if (baud) +#ifdef CONFIG_AR7 -+ quot = get_avalanche_vbus_freq() / baud; -+ -+ if ((quot%16)>7) -+ quot += 8; -+ quot /=16; ++ flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x200); +#else - quot = baud_base / baud; + flush_icache_range(KSEG0, KSEG0 + 0x400); +#endif - } - /* If the quotient is zero refuse the change */ - if (!quot && old_termios) { -@@ -5552,8 +5595,10 @@ - state->irq = irq_cannonicalize(state->irq); - if (state->hub6) - state->io_type = SERIAL_IO_HUB6; + + per_cpu_trap_init(); + } +diff -urN kernel-base/arch/mips/lib/promlib.c kernel-current/arch/mips/lib/promlib.c +--- kernel-base/arch/mips/lib/promlib.c 2005-07-10 03:00:44.786181072 +0200 ++++ kernel-current/arch/mips/lib/promlib.c 2005-07-10 06:40:39.591265000 +0200 +@@ -1,3 +1,4 @@ +#ifndef CONFIG_AR7 - if (state->port && check_region(state->port,8)) - continue; -+#endif - #ifdef CONFIG_MCA - if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus) - continue; -@@ -6009,7 +6054,15 @@ - info->io_type = state->io_type; - info->iomem_base = state->iomem_base; - info->iomem_reg_shift = state->iomem_reg_shift; -+#ifdef CONFIG_AR7 -+ quot = get_avalanche_vbus_freq() / baud; -+ -+ if ((quot%16)>7) -+ quot += 8; -+ quot /=16; -+#else - quot = state->baud_base / baud; -+#endif - cval = cflag & (CSIZE | CSTOPB); - #if defined(__powerpc__) || defined(__alpha__) - cval >>= 8; -diff -urN linux.old/include/asm-mips/ar7/ar7.h linux.dev/include/asm-mips/ar7/ar7.h ---- linux.old/include/asm-mips/ar7/ar7.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/ar7/ar7.h 2005-07-07 04:39:14.430224000 +0200 -@@ -0,0 +1,137 @@ -+#ifndef _MIPS_AR7_H -+#define _MIPS_AR7_H -+ -+#include -+#include -+ -+ -+#ifndef LITTLE_ENDIAN -+#define LITTLE_ENDIAN -+#endif -+ -+#ifndef _LINK_KSEG0_ -+#define _LINK_KSEG0_ -+#endif -+ -+#include -+ -+#define AVALANCHE_UART0_INT 7 -+#define AVALANCHE_UART1_INT 8 -+ -+#define MIPS_EXCEPTION_OFFSET 8 -+#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET) -+ -+/* -+ * AR7 board SDRAM base address. This is used to setup the -+ * bootmem tables -+ */ -+ -+#define AVALANCHE_SDRAM_BASE CONFIG_AR7_MEMORY//0x14000000UL -+#define AVALANCHE_INTC_BASE TNETD73XX_INTC_BASE -+ -+ -+/* -+ * AR7 board vectors -+ */ -+ -+#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE)) -+#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE)) -+ -+ -+/* -+ * Yamon Prom print address. -+ */ -+#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500)) -+#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */ -+#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34) -+ -+/* -+ * AR7 Reset and PSU standby register. -+ */ -+#define AVALANCHE_SOFTRES_REG (KSEG1ADDR(0x08611600)) /* Resets machine */ -+#define AVALANCHE_PSUSTBY_REG (KSEG1ADDR(0x08611600)) /* Turns off power supply unit */ -+#define AVALANCHE_GORESET 0x1 -+#define AVALANCHE_GOSTBY 0x1 -+#define AVALANCHE_SWRCR (*(unsigned int *)TNETD73XX_RST_CTRL_SWRCR) -+ -+/* -+ * Avalanche UART register base. -+ */ -+ -+#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */ -+#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 1 */ -+#define AVALANCHE_BASE_BAUD ( 3686400 / 16 ) -+ -+/* -+ * AVALANCHE DMA controller base -+ */ -+ -+#define AVALANCHE_DMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* DMA 0 (channels 0-3) */ -+ -+ -+ -+/* -+ * GPIO register map -+ */ -+ -+/* to be obtained from avalanche_map.h */ -+#define AVALANCHE_GPIO_WRITE_REG (KSEG1ADDR(0xa8610904)) -+#define AVALANCHE_GPIO_DIRECTION_REG (KSEG1ADDR(0xa8610908)) -+#define AVALANCHE_GPIO_MODE_REG (KSEG1ADDR(0xa861090C)) -+#define AVALANCHE_GPIO_PIN_COUNT 32 -+#define AVALANCHE_GPIO_OFF_MAP {0xF34FFFC0,0} -+ -+ -+// Let us define board specific information here. -+ -+#if defined(CONFIG_AR7DB) -+ -+#define AFECLK_FREQ 35328000 -+#define REFCLK_FREQ 25000000 -+#define OSC3_FREQ 24000000 -+#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000 -+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x55555555 -+ + #include + #include + +@@ -22,3 +23,4 @@ + } + va_end(args); + } +#endif +diff -urN kernel-base/arch/mips/Makefile kernel-current/arch/mips/Makefile +--- kernel-base/arch/mips/Makefile 2005-07-10 03:00:44.786181072 +0200 ++++ kernel-current/arch/mips/Makefile 2005-07-10 06:40:39.591265000 +0200 +@@ -369,6 +369,16 @@ + endif + + # ++# Texas Instruments AR7 ++# + ++ifdef CONFIG_AR7 ++LIBS += arch/mips/ar7/ar7.o arch/mips/ar7/ar7/ar7.o ++SUBDIRS += arch/mips/ar7 arch/mips/ar7/ar7 ++LOADADDR += 0x94020000 ++endif + -+#if defined(CONFIG_AR7RD) -+ -+#define AFECLK_FREQ 35328000 -+#define REFCLK_FREQ 25000000 -+#define OSC3_FREQ 24000000 -+#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000 -+ -+#if defined(CONFIG_AR7_MARVELL) -+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000 -+#else -+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2 ++# + # DECstation family + # + ifdef CONFIG_DECSTATION +diff -urN kernel-base/arch/mips/mm/init.c kernel-current/arch/mips/mm/init.c +--- kernel-base/arch/mips/mm/init.c 2005-07-10 03:00:44.787180920 +0200 ++++ kernel-current/arch/mips/mm/init.c 2005-07-10 07:09:29.914216000 +0200 +@@ -40,8 +40,10 @@ + + mmu_gather_t mmu_gathers[NR_CPUS]; + unsigned long highstart_pfn, highend_pfn; ++#ifndef CONFIG_AR7_PAGING + static unsigned long totalram_pages; + static unsigned long totalhigh_pages; +#endif -+ + + void pgd_init(unsigned long page) + { +@@ -235,6 +237,7 @@ + #endif + } + ++#ifndef CONFIG_AR7_PAGING + void __init paging_init(void) + { + unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0}; +@@ -272,6 +275,7 @@ + + free_area_init(zones_size); + } +#endif -+ -+ -+#if defined(CONFIG_AR7WRD) -+ -+#define AFECLK_FREQ 35328000 -+#define REFCLK_FREQ 25000000 -+#define OSC3_FREQ 24000000 -+#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000 -+ -+#if defined(CONFIG_AR7_MARVELL) -+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000 -+#else -+#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2 + + #define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT) + #define PFN_DOWN(x) ((x) >> PAGE_SHIFT) +@@ -298,6 +302,7 @@ + return 0; + } + ++#ifndef CONFIG_AR7_PAGING + void __init mem_init(void) + { + unsigned long codesize, reservedpages, datasize, initsize; +@@ -359,6 +364,7 @@ + initsize >> 10, + (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10))); + } +#endif -+ + + #ifdef CONFIG_BLK_DEV_INITRD + void free_initrd_mem(unsigned long start, unsigned long end) +@@ -376,6 +382,7 @@ + } + #endif + ++#ifndef CONFIG_AR7_PAGING + extern char __init_begin, __init_end; + extern void prom_free_prom_memory(void) __init; + +@@ -383,7 +390,9 @@ + { + unsigned long addr; + ++#ifndef CONFIG_AR7 + prom_free_prom_memory (); ++#endif + + addr = (unsigned long) &__init_begin; + while (addr < (unsigned long) &__init_end) { +@@ -409,3 +418,4 @@ + + return; + } ++#endif +diff -urN kernel-base/arch/mips/mm/tlb-r4k.c kernel-current/arch/mips/mm/tlb-r4k.c +--- kernel-base/arch/mips/mm/tlb-r4k.c 2005-07-10 03:00:44.787180920 +0200 ++++ kernel-current/arch/mips/mm/tlb-r4k.c 2005-07-10 06:40:39.592265000 +0200 +@@ -20,6 +20,10 @@ + #include + #include + ++#ifdef CONFIG_AR7 ++#include +#endif + -+extern unsigned int tnetd73xx_vbus_freq; -+#define AVALANCHE_VBUS_FREQ tnetd73xx_vbus_freq -+ -+static inline unsigned int get_avalanche_vbus_freq(void) -+{ -+ return (tnetd73xx_vbus_freq); -+} -+ -+#endif /*_MIPS_AR7_H */ -diff -urN linux.old/include/asm-mips/ar7/avalanche.h linux.dev/include/asm-mips/ar7/avalanche.h ---- linux.old/include/asm-mips/ar7/avalanche.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/ar7/avalanche.h 2005-07-07 04:39:14.430224000 +0200 -@@ -0,0 +1,183 @@ -+/* $Id$ -+ * -+ * avalanche.h -+ * -+ * Jeff Harrell, jharrell@ti.com -+ * Copyright (C) 2000,2001,2002 Texas Instruments Inc. -+ * -+ * -+ * ######################################################################## -+ * -+ * This program is free software; you can distribute it and/or modify it -+ * under the terms of the GNU General Public License (Version 2) as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * for more details. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -+ * -+ * ######################################################################## -+ * -+ * Defines of the AVALANCHE board specific address-MAP, registers, etc. -+ * -+ */ -+#ifndef _MIPS_AVALANCHE_H -+#define _MIPS_AVALANCHE_H -+ -+#include -+ -+/* -+ * AVALANCHE board SDRAM base address. This is used to setup the -+ * bootmem tables -+ */ -+ -+#define AVALANCHE_SDRAM_BASE 0x14000000UL -+ -+/* -+ * AVALANCHE board vectors -+ */ -+ -+#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE)) -+#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE)) -+/* -+ * Avalanche RTC-device indirect register access. -+ */ -+ -+#define EVM3_RTC_ADR_REG (KSEG1ADDR(0x1f000800)) -+#define EVM3_RTC_DAT_REG (KSEG1ADDR(0x1f000808)) -+ -+/* -+ * Evm3 interrupt controller register base (primary) -+ */ -+ -+#define AVALANCHE_ICTRL_REGS_BASE (KSEG1ADDR(0x08612400)) -+ -+/* -+ * Avalanche exception controller register base (secondary) -+ */ -+#define AVALANCHE_ECTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE+0x80) -+ -+ -+/* -+ * Avalanche Interrupt Channel Control register base -+ */ -+#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200) -+ -+ -+/* -+ * Avalanche UART register base. -+ */ + extern char except_vec0_nevada, except_vec0_r4000, except_vec0_r4600; + + /* CP0 hazard avoidance. */ +@@ -375,7 +379,12 @@ + else if (current_cpu_data.cputype == CPU_R4600) + memcpy((void *)KSEG0, &except_vec0_r4600, 0x80); + else ++#ifdef CONFIG_AR7 ++ memcpy((void *)AVALANCHE_VECS_KSEG0, &except_vec0_r4000, 0x80); ++ flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x80); ++#else + memcpy((void *)KSEG0, &except_vec0_r4000, 0x80); + flush_icache_range(KSEG0, KSEG0 + 0x80); ++#endif + } + } +diff -urN kernel-base/drivers/char/serial.c kernel-current/drivers/char/serial.c +--- kernel-base/drivers/char/serial.c 2005-07-10 03:00:44.789180616 +0200 ++++ kernel-current/drivers/char/serial.c 2005-07-10 06:42:02.902600000 +0200 +@@ -419,7 +419,40 @@ + return 0; + } + +-#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD) ++#if defined(CONFIG_AR7) + -+#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */ -+#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 1 */ -+#define AVALANCHE_BASE_BAUD ( 3686400 / 16 ) -+/* -+ * AVALANCHE DMA controller base -+ */ ++static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset) ++{ ++ return (inb(info->port + (offset * 4)) & 0xff); ++} + -+#define AVALANCHE_DMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* DMA 0 (channels 0-3) */ + ++static _INLINE_ unsigned int serial_inp(struct async_struct *info, int offset) ++{ ++#ifdef CONFIG_SERIAL_NOPAUSE_IO ++ return (inb(info->port + (offset * 4)) & 0xff); ++#else ++ return (inb_p(info->port + (offset * 4)) & 0xff); ++#endif ++} + -+/* -+ * AVALANCHE display register base. -+ */ ++static _INLINE_ void serial_out(struct async_struct *info, int offset, int value) ++{ ++ outb(value, info->port + (offset * 4)); ++} + -+#define EVM3_ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1D000038)) -+#define EVM3_ASCII_DISPLAY_WORD_BASE (KSEG1ADDR(0x1D00003F)) /* How is this used??? JAH */ + ++static _INLINE_ void serial_outp(struct async_struct *info, int offset, ++ int value) ++{ ++#ifdef CONFIG_SERIAL_NOPAUSE_IO ++ outb(value, info->port + (offset * 4)); ++#else ++ outb_p(value, info->port + (offset * 4)); ++#endif ++} + -+#define EVM3_ASCIIPOS0 0x1D000038 -+#define EVM3_ASCIIPOS1 0x1D000039 -+#define EVM3_ASCIIPOS2 0x1D00003A -+#define EVM3_ASCIIPOS3 0x1D00003B -+#define EVM3_ASCIIPOS4 0x1D00003C -+#define EVM3_ASCIIPOS5 0x1D00003D -+#define EVM3_ASCIIPOS6 0x1D00003E -+#define EVM3_ASCIIPOS7 0x1D00003F ++#elif defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD) + + #include + +@@ -478,8 +511,10 @@ + * needed for certain old 386 machines, I've left these #define's + * in.... + */ ++#ifndef CONFIG_AR7 + #define serial_inp(info, offset) serial_in(info, offset) + #define serial_outp(info, offset, value) serial_out(info, offset, value) ++#endif + + + /* +@@ -1728,7 +1763,16 @@ + /* Special case since 134 is really 134.5 */ + quot = (2*baud_base / 269); + else if (baud) ++#ifdef CONFIG_AR7 ++ quot = (CONFIG_AR7_SYS_FREQUENCY*500000) / baud; ++ //quot = get_avalanche_vbus_freq() / baud; + -+/* -+ * Yamon Prom print address. -+ */ -+#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500)) -+#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */ -+#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34) ++ if ((quot%16)>7) ++ quot += 8; ++ quot /=16; ++#else + quot = baud_base / baud; ++#endif + } + /* If the quotient is zero refuse the change */ + if (!quot && old_termios) { +@@ -5552,8 +5596,10 @@ + state->irq = irq_cannonicalize(state->irq); + if (state->hub6) + state->io_type = SERIAL_IO_HUB6; ++#ifndef CONFIG_AR7 + if (state->port && check_region(state->port,8)) + continue; ++#endif + #ifdef CONFIG_MCA + if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus) + continue; +@@ -6009,7 +6055,16 @@ + info->io_type = state->io_type; + info->iomem_base = state->iomem_base; + info->iomem_reg_shift = state->iomem_reg_shift; ++#ifdef CONFIG_AR7 ++ //quot = get_avalanche_vbus_freq() / baud; ++ quot = (CONFIG_AR7_SYS_FREQUENCY*500000) / baud; + ++ if ((quot%16)>7) ++ quot += 8; ++ quot /=16; ++#else + quot = state->baud_base / baud; ++#endif + cval = cflag & (CSIZE | CSTOPB); + #if defined(__powerpc__) || defined(__alpha__) + cval >>= 8; +diff -urN kernel-base/include/asm-mips/ar7/ar7.h kernel-current/include/asm-mips/ar7/ar7.h +--- kernel-base/include/asm-mips/ar7/ar7.h 1970-01-01 01:00:00.000000000 +0100 ++++ kernel-current/include/asm-mips/ar7/ar7.h 2005-07-10 06:40:39.622261000 +0200 +@@ -0,0 +1,33 @@ +/* -+ * Evm3 Reset and PSU standby register. ++ * $Id$ ++ * Copyright (C) $Date$ $Author$ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ * + */ -+#define AVALANCHE_SOFTRES_REG (KSEG1ADDR(0x08611600)) /* Resets machine */ -+#define AVALANCHE_PSUSTBY_REG (KSEG1ADDR(0x08611600)) /* Turns off power supply unit */ -+#define AVALANCHE_GORESET 0x1 -+#define AVALANCHE_GOSTBY 0x1 -+ -+/************************************************************************ -+ * PERIPHERAL BUS LEDs (P-LED): -+*************************************************************************/ -+ -+/************************************************************************ -+ * P-LED Register Addresses -+*************************************************************************/ -+ -+#define EVM3_PLED (KSEG1ADDR(0x01C500000)) /* 0x1D200000 P-LED */ -+ -+ -+/************************************************************************ -+ * Register field encodings -+*************************************************************************/ -+ -+/******** reg: PLED ********/ -+/* bits 7:0: VAL */ -+#define EVM3_PLED_VAL_MSK 0xff -+ -+/* bit 0: */ -+#define EVM3_PLED_BIT0_SHF 0 -+#define EVM3_PLED_BIT0_MSK (1 << EVM3_PLED_BIT0_SHF) -+#define EVM3_PLED_BIT0_ON EVM3_PLED_BIT0_MSK -+ -+/* bit 1: */ -+#define EVM3_PLED_BIT1_SHF 1 -+#define EVM3_PLED_BIT1_MSK (1 << EVM3_PLED_BIT1_SHF) -+#define EVM3_PLED_BIT1_ON EVM3_PLED_BIT1_MSK -+ -+/* bit 2: */ -+#define EVM3_PLED_BIT2_SHF 2 -+#define EVM3_PLED_BIT2_MSK (1 << EVM3_PLED_BIT2_SHF) -+#define EVM3_PLED_BIT2_ON EVM3_PLED_BIT2_MSK -+ -+/* bit 3: */ -+#define EVM3_PLED_BIT3_SHF 3 -+#define EVM3_PLED_BIT3_MSK (1 << EVM3_PLED_BIT3_SHF) -+#define EVM3_PLED_BIT3_ON EVM3_PLED_BIT3_MSK -+ -+/* bit 4: */ -+#define EVM3_PLED_BIT4_SHF 4 -+#define EVM3_PLED_BIT4_MSK (1 << EVM3_PLED_BIT4_SHF) -+#define EVM3_PLED_BIT4_ON EVM3_PLED_BIT4_MSK -+ -+/* bit 5: */ -+#define EVM3_PLED_BIT5_SHF 5 -+#define EVM3_PLED_BIT5_MSK (1 << EVM3_PLED_BIT5_SHF) -+#define EVM3_PLED_BIT5_ON EVM3_PLED_BIT5_MSK -+ -+/* bit 6: */ -+#define EVM3_PLED_BIT6_SHF 6 -+#define EVM3_PLED_BIT6_MSK (1 << EVM3_PLED_BIT6_SHF) -+#define EVM3_PLED_BIT6_ON EVM3_PLED_BIT6_MSK -+ -+/* bit 7: */ -+#define EVM3_PLED_BIT7_SHF 7 -+#define EVM3_PLED_BIT7_MSK (1 << EVM3_PLED_BIT7_SHF) -+#define EVM3_PLED_BIT7_ON EVM3_PLED_BIT7_MSK -+ -+#endif /* !(_MIPS_AVALANCHE_H) */ -+ + ++#ifndef _AR7_H ++#define _AR7_H + ++#include ++#include + ++#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(CONFIG_AR7_MEMORY)) + ++#define AR7_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) ++#define AR7_UART1_REGS_BASE (KSEG1ADDR(0x08610E00)) ++#define AR7_BASE_BAUD ( 3686400 / 16 ) + -diff -urN linux.old/include/asm-mips/ar7/avalanche_intc.h linux.dev/include/asm-mips/ar7/avalanche_intc.h ---- linux.old/include/asm-mips/ar7/avalanche_intc.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/ar7/avalanche_intc.h 2005-07-07 04:39:14.431224000 +0200 -@@ -0,0 +1,273 @@ ++#endif +diff -urN kernel-base/include/asm-mips/ar7/avalanche_intc.h kernel-current/include/asm-mips/ar7/avalanche_intc.h +--- kernel-base/include/asm-mips/ar7/avalanche_intc.h 1970-01-01 01:00:00.000000000 +0100 ++++ kernel-current/include/asm-mips/ar7/avalanche_intc.h 2005-07-10 06:40:39.622261000 +0200 +@@ -0,0 +1,278 @@ + /* + * Nitin Dhingra, iamnd@ti.com + * Copyright (C) 2000 Texas Instruments Inc. @@ -3795,7 +2973,12 @@ diff -urN linux.old/include/asm-mips/ar7/avalanche_intc.h linux.dev/include/asm- +/* + * Avalanche interrupt controller register base (primary) + */ -+#define AVALANCHE_ICTRL_REGS_BASE AVALANCHE_INTC_BASE ++#define KSEG1_BASE 0xA0000000 ++#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */ ++#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK) ++#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE) ++ ++#define AVALANCHE_ICTRL_REGS_BASE KSEG1ADDR(0x08612400)// AVALANCHE_INTC_BASE + +/****************************************************************************** + * Avalanche exception controller register base (secondary) @@ -4011,369 +3194,187 @@ diff -urN linux.old/include/asm-mips/ar7/avalanche_intc.h linux.dev/include/asm- + + +#endif /* _AVALANCHE_INTC_H */ -diff -urN linux.old/include/asm-mips/ar7/avalanche_int.h linux.dev/include/asm-mips/ar7/avalanche_int.h ---- linux.old/include/asm-mips/ar7/avalanche_int.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/ar7/avalanche_int.h 2005-07-07 04:39:14.431224000 +0200 -@@ -0,0 +1,298 @@ -+/* $Id$ -+ * -+ * avalancheint.h -+ * -+ * Jeff Harrell, jharrell@ti.com -+ * Copyright (C) 2000,2001 Texas Instruments , Inc. -+ * -+ * ######################################################################## -+ * -+ * This program is free software; you can distribute it and/or modify it -+ * under the terms of the GNU General Public License (Version 2) as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * for more details. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -+ * -+ * ######################################################################## -+ * -+ * Defines for the AVALANCHE interrupt controller. -+ * -+ */ -+#ifndef _MIPS_AVALANCHEINT_H -+#define _MIPS_AVALANCHEINT_H -+ -+#include -+ -+/* Avalanche Interrupt number */ -+#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET) -+/* Linux Interrupt number */ -+#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET) -+/* Number of IRQ supported on hw interrupt 0. */ -+ -+//#define SEADINT_UART0 3 /* TTYS0 interrupt on SEAD */ -+//#define SEADINT_UART1 4 /* TTYS1 interrupt on SEAD */ -+ +diff -urN kernel-base/include/asm-mips/ar7/avalanche_misc.h kernel-current/include/asm-mips/ar7/avalanche_misc.h +--- kernel-base/include/asm-mips/ar7/avalanche_misc.h 1970-01-01 01:00:00.000000000 +0100 ++++ kernel-current/include/asm-mips/ar7/avalanche_misc.h 2005-07-10 18:45:35.089287296 +0200 +@@ -0,0 +1,174 @@ ++#ifndef _AVALANCHE_MISC_H_ ++#define _AVALANCHE_MISC_H_ ++ ++typedef enum AVALANCHE_ERR_t ++{ ++ AVALANCHE_ERR_OK = 0, /* OK or SUCCESS */ ++ AVALANCHE_ERR_ERROR = -1, /* Unspecified/Generic ERROR */ + -+#define MIPS_EXCEPTION_OFFSET 8 -+#define AVALANCHE_INT_END_PRIMARY (40 + MIPS_EXCEPTION_OFFSET) -+#define AVALANCHE_INT_END_SECONDARY (32 + MIPS_EXCEPTION_OFFSET) ++ /* Pointers and args */ ++ AVALANCHE_ERR_INVARG = -2, /* Invaild argument to the call */ ++ AVALANCHE_ERR_NULLPTR = -3, /* NULL pointer */ ++ AVALANCHE_ERR_BADPTR = -4, /* Bad (out of mem) pointer */ + -+#define AVALANCHE_INT_END_PRIMARY_REG1 (31 + MIPS_EXCEPTION_OFFSET) -+#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET) ++ /* Memory issues */ ++ AVALANCHE_ERR_ALLOC_FAIL = -10, /* allocation failed */ ++ AVALANCHE_ERR_FREE_FAIL = -11, /* free failed */ ++ AVALANCHE_ERR_MEM_CORRUPT = -12, /* corrupted memory */ ++ AVALANCHE_ERR_BUF_LINK = -13, /* buffer linking failed */ + ++ /* Device issues */ ++ AVALANCHE_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */ ++ AVALANCHE_ERR_DEVICE_MALFUNC = -21, /* device malfunction */ + -+#define AVALANCHE_INT_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + AVINTNUM(AVALANCHE_INT_END_SECONDARY) \ -+ + MIPS_EXCEPTION_OFFSET - 1) ++ AVALANCHE_ERR_INVID = -30 /* Invalid ID */ + -+struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */ -+{ -+ volatile unsigned long intsr1; /* Interrupt Status/Set Register 1 */ /* 0x00 */ -+ volatile unsigned long intsr2; /* Interrupt Status/Set Register 2 */ /* 0x04 */ -+ volatile unsigned long unused1; /* 0x08 */ -+ volatile unsigned long unused2; /* 0x0C */ -+ volatile unsigned long intcr1; /* Interrupt Clear Register 1 */ /* 0x10 */ -+ volatile unsigned long intcr2; /* Interrupt Clear Register 2 */ /* 0x14 */ -+ volatile unsigned long unused3; /* 0x18 */ -+ volatile unsigned long unused4; /* 0x1C */ -+ volatile unsigned long intesr1; /* Interrupt Enable (Set) Register 1 */ /* 0x20 */ -+ volatile unsigned long intesr2; /* Interrupt Enable (Set) Register 2 */ /* 0x24 */ -+ volatile unsigned long unused5; /* 0x28 */ -+ volatile unsigned long unused6; /* 0x2C */ -+ volatile unsigned long intecr1; /* Interrupt Enable Clear Register 1 */ /* 0x30 */ -+ volatile unsigned long intecr2; /* Interrupt Enable Clear Register 2 */ /* 0x34 */ -+ volatile unsigned long unused7; /* 0x38 */ -+ volatile unsigned long unused8; /* 0x3c */ -+ volatile unsigned long pintir; /* Priority Interrupt Index Register */ /* 0x40 */ -+ volatile unsigned long intmsr; /* Priority Interrupt Mask Index Reg.*/ /* 0x44 */ -+ volatile unsigned long unused9; /* 0x48 */ -+ volatile unsigned long unused10; /* 0x4C */ -+ volatile unsigned long intpolr1; /* Interrupt Polarity Mask register 1*/ /* 0x50 */ -+ volatile unsigned long intpolr2; /* Interrupt Polarity Mask register 2*/ /* 0x54 */ -+}; ++} AVALANCHE_ERR; + -+struct avalanche_exctrl_regs /* Avalanche Exception control registers */ -+{ -+ volatile unsigned long exsr; /* Exceptions Status/Set register */ /* 0x80 */ -+ volatile unsigned long reserved; /* 0x84 */ -+ volatile unsigned long excr; /* Exceptions Clear Register */ /* 0x88 */ -+ volatile unsigned long reserved1; /* 0x8c */ -+ volatile unsigned long exiesr; /* Exceptions Interrupt Enable (set) */ /* 0x90 */ -+ volatile unsigned long reserved2; /* 0x94 */ -+ volatile unsigned long exiecr; /* Exceptions Interrupt Enable (clear)*/ /* 0x98 */ -+}; ++/***************************************************************************** ++ * Reset Control Module ++ *****************************************************************************/ + -+struct avalanche_channel_int_number ++typedef enum AVALANCHE_RESET_MODULE_tag +{ -+ volatile unsigned long cintnr0; /* Channel Interrupt Number Register */ /* 0x200 */ -+ volatile unsigned long cintnr1; /* Channel Interrupt Number Register */ /* 0x204 */ -+ volatile unsigned long cintnr2; /* Channel Interrupt Number Register */ /* 0x208 */ -+ volatile unsigned long cintnr3; /* Channel Interrupt Number Register */ /* 0x20C */ -+ volatile unsigned long cintnr4; /* Channel Interrupt Number Register */ /* 0x210 */ -+ volatile unsigned long cintnr5; /* Channel Interrupt Number Register */ /* 0x214 */ -+ volatile unsigned long cintnr6; /* Channel Interrupt Number Register */ /* 0x218 */ -+ volatile unsigned long cintnr7; /* Channel Interrupt Number Register */ /* 0x21C */ -+ volatile unsigned long cintnr8; /* Channel Interrupt Number Register */ /* 0x220 */ -+ volatile unsigned long cintnr9; /* Channel Interrupt Number Register */ /* 0x224 */ -+ volatile unsigned long cintnr10; /* Channel Interrupt Number Register */ /* 0x228 */ -+ volatile unsigned long cintnr11; /* Channel Interrupt Number Register */ /* 0x22C */ -+ volatile unsigned long cintnr12; /* Channel Interrupt Number Register */ /* 0x230 */ -+ volatile unsigned long cintnr13; /* Channel Interrupt Number Register */ /* 0x234 */ -+ volatile unsigned long cintnr14; /* Channel Interrupt Number Register */ /* 0x238 */ -+ volatile unsigned long cintnr15; /* Channel Interrupt Number Register */ /* 0x23C */ -+ volatile unsigned long cintnr16; /* Channel Interrupt Number Register */ /* 0x240 */ -+ volatile unsigned long cintnr17; /* Channel Interrupt Number Register */ /* 0x244 */ -+ volatile unsigned long cintnr18; /* Channel Interrupt Number Register */ /* 0x248 */ -+ volatile unsigned long cintnr19; /* Channel Interrupt Number Register */ /* 0x24C */ -+ volatile unsigned long cintnr20; /* Channel Interrupt Number Register */ /* 0x250 */ -+ volatile unsigned long cintnr21; /* Channel Interrupt Number Register */ /* 0x254 */ -+ volatile unsigned long cintnr22; /* Channel Interrupt Number Register */ /* 0x358 */ -+ volatile unsigned long cintnr23; /* Channel Interrupt Number Register */ /* 0x35C */ -+ volatile unsigned long cintnr24; /* Channel Interrupt Number Register */ /* 0x260 */ -+ volatile unsigned long cintnr25; /* Channel Interrupt Number Register */ /* 0x264 */ -+ volatile unsigned long cintnr26; /* Channel Interrupt Number Register */ /* 0x268 */ -+ volatile unsigned long cintnr27; /* Channel Interrupt Number Register */ /* 0x26C */ -+ volatile unsigned long cintnr28; /* Channel Interrupt Number Register */ /* 0x270 */ -+ volatile unsigned long cintnr29; /* Channel Interrupt Number Register */ /* 0x274 */ -+ volatile unsigned long cintnr30; /* Channel Interrupt Number Register */ /* 0x278 */ -+ volatile unsigned long cintnr31; /* Channel Interrupt Number Register */ /* 0x27C */ -+ volatile unsigned long cintnr32; /* Channel Interrupt Number Register */ /* 0x280 */ -+ volatile unsigned long cintnr33; /* Channel Interrupt Number Register */ /* 0x284 */ -+ volatile unsigned long cintnr34; /* Channel Interrupt Number Register */ /* 0x288 */ -+ volatile unsigned long cintnr35; /* Channel Interrupt Number Register */ /* 0x28C */ -+ volatile unsigned long cintnr36; /* Channel Interrupt Number Register */ /* 0x290 */ -+ volatile unsigned long cintnr37; /* Channel Interrupt Number Register */ /* 0x294 */ -+ volatile unsigned long cintnr38; /* Channel Interrupt Number Register */ /* 0x298 */ -+ volatile unsigned long cintnr39; /* Channel Interrupt Number Register */ /* 0x29C */ -+}; ++ RESET_MODULE_UART0 = 0, ++ RESET_MODULE_UART1 = 1, ++ RESET_MODULE_I2C = 2, ++ RESET_MODULE_TIMER0 = 3, ++ RESET_MODULE_TIMER1 = 4, ++ RESET_MODULE_GPIO = 6, ++ RESET_MODULE_ADSLSS = 7, ++ RESET_MODULE_USBS = 8, ++ RESET_MODULE_SAR = 9, ++ RESET_MODULE_VDMA_VT = 11, ++ RESET_MODULE_FSER = 12, ++ RESET_MODULE_VLYNQ1 = 16, ++ RESET_MODULE_EMAC0 = 17, ++ RESET_MODULE_DMA = 18, ++ RESET_MODULE_BIST = 19, ++ RESET_MODULE_VLYNQ0 = 20, ++ RESET_MODULE_EMAC1 = 21, ++ RESET_MODULE_MDIO = 22, ++ RESET_MODULE_ADSLSS_DSP = 23, ++ RESET_MODULE_EPHY = 26 ++} AVALANCHE_RESET_MODULE_T; + -+struct avalanche_interrupt_line_to_channel ++typedef enum AVALANCHE_RESET_CTRL_tag +{ -+ unsigned long int_line0; /* Start of primary interrupts */ -+ unsigned long int_line1; -+ unsigned long int_line2; -+ unsigned long int_line3; -+ unsigned long int_line4; -+ unsigned long int_line5; -+ unsigned long int_line6; -+ unsigned long int_line7; -+ unsigned long int_line8; -+ unsigned long int_line9; -+ unsigned long int_line10; -+ unsigned long int_line11; -+ unsigned long int_line12; -+ unsigned long int_line13; -+ unsigned long int_line14; -+ unsigned long int_line15; -+ unsigned long int_line16; -+ unsigned long int_line17; -+ unsigned long int_line18; -+ unsigned long int_line19; -+ unsigned long int_line20; -+ unsigned long int_line21; -+ unsigned long int_line22; -+ unsigned long int_line23; -+ unsigned long int_line24; -+ unsigned long int_line25; -+ unsigned long int_line26; -+ unsigned long int_line27; -+ unsigned long int_line28; -+ unsigned long int_line29; -+ unsigned long int_line30; -+ unsigned long int_line31; -+ unsigned long int_line32; -+ unsigned long int_line33; -+ unsigned long int_line34; -+ unsigned long int_line35; -+ unsigned long int_line36; -+ unsigned long int_line37; -+ unsigned long int_line38; -+ unsigned long int_line39; -+}; -+ -+/* Interrupt Line #'s (Avalanche peripherals) */ ++ IN_RESET = 0, ++ OUT_OF_RESET ++} AVALANCHE_RESET_CTRL_T; + -+/*------------------------------*/ -+/* Avalanche primary interrupts */ -+/*------------------------------*/ -+#define UNIFIED_SECONDARY_INTERRUPT 0 -+#define AVALANCHE_EXT_INT_0 1 -+#define AVALANCHE_EXT_INT_1 2 -+#define AVALANCHE_EXT_INT_2 3 -+#define AVALANCHE_EXT_INT_3 4 -+#define AVALANCHE_TIMER_0_INT 5 -+#define AVALANCHE_TIMER_1_INT 6 -+#define AVALANCHE_UART0_INT 7 -+#define AVALANCHE_UART1_INT 8 -+#define AVALANCHE_PDMA_INT0 9 -+#define AVALANCHE_PDMA_INT1 10 -+#define AVALANCHE_HDLC_TXA 11 -+#define AVALANCHE_HDLC_TXB 12 -+#define AVALANCHE_HDLC_RXA 13 -+#define AVALANCHE_HDLC_RXB 14 -+#define AVALANCHE_ATM_SAR_TXA 15 -+#define AVALANCHE_ATM_SAR_TXB 16 -+#define AVALANCHE_ATM_SAR_RXA 17 -+#define AVALANCHE_ATM_SAR_RXB 18 -+#define AVALANCHE_MAC_TXA 19 -+#define AVALANCHE_MAC_RXA 20 -+#define AVALANCHE_DSP_SUB0 21 -+#define AVALANCHE_DSP_SUB1 22 -+#define AVALANCHE_DES_INT 23 -+#define AVALANCHE_USB_INT 24 -+#define AVALANCHE_PCI_INTA 25 -+#define AVALANCHE_PCI_INTB 26 -+#define AVALANCHE_PCI_INTC 27 -+/* Line #28 Reserved */ -+#define AVALANCHE_I2CM_INT 29 -+#define AVALANCHE_PDMA_INT2 30 -+#define AVALANCHE_PDMA_INT3 31 -+#define AVALANCHE_CODEC 32 -+#define AVALANCHE_MAC_TXB 33 -+#define AVALANCHE_MAC_RXB 34 -+/* Line #35 Reserved */ -+/* Line #36 Reserved */ -+/* Line #37 Reserved */ -+/* Line #38 Reserved */ -+/* Line #39 Reserved */ ++typedef enum AVALANCHE_SYS_RST_MODE_tag ++{ ++ RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */ ++ RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */ ++} AVALANCHE_SYS_RST_MODE_T; ++ ++typedef enum AVALANCHE_SYS_RESET_STATUS_tag ++{ ++ HARDWARE_RESET = 0, ++ SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */ ++ WATCHDOG_RESET, ++ SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */ ++} AVALANCHE_SYS_RESET_STATUS_T; ++ ++AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(AVALANCHE_RESET_MODULE_T reset_module); ++void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode); ++AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status(void); + -+#define DEBUG_MISSED_INTS 1 ++typedef int (*REMOTE_VLYNQ_DEV_RESET_CTRL_FN)(unsigned int reset_module, AVALANCHE_RESET_CTRL_T reset_ctrl); ++ ++/***************************************************************************** ++ * Power Control Module ++ *****************************************************************************/ + -+#ifdef DEBUG_MISSED_INTS -+struct debug_missed_int ++typedef enum AVALANCHE_POWER_CTRL_tag +{ -+ unsigned int atm_sar_txa; -+ unsigned int atm_sar_txb; -+ unsigned int atm_sar_rxa; -+ unsigned int atm_sar_rxb; -+ unsigned int mac_txa; -+ unsigned int mac_rxa; -+ unsigned int mac_txb; -+ unsigned int mac_rxb; -+}; -+#endif /* DEBUG_MISSED_INTS */ ++ POWER_CTRL_POWER_UP = 0, ++ POWER_CTRL_POWER_DOWN ++} AVALANCHE_POWER_CTRL_T; + -+/*-----------------------------------*/ -+/* Avalanche Secondary Interrupts */ -+/*-----------------------------------*/ -+#define PRIMARY_INTS 40 ++typedef enum AVALANCHE_SYS_POWER_MODE_tag ++{ ++ GLOBAL_POWER_MODE_RUN = 0, /* All system is up */ ++ GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */ ++ GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */ ++ GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */ ++} AVALANCHE_SYS_POWER_MODE_T; + -+#define AVALANCHE_HDLC_STATUS (0 + PRIMARY_INTS) -+#define AVALANCHE_SAR_STATUS (1 + PRIMARY_INTS) -+/* Line #02 Reserved */ -+#define AVALANCHE_ETH_MACA_LNK_CHG (3 + PRIMARY_INTS) -+#define AVALANCHE_ETH_MACA_MGT (4 + PRIMARY_INTS) -+#define AVALANCHE_PCI_STATUS_INT (5 + PRIMARY_INTS) -+/* Line #06 Reserved */ -+#define AVALANCHE_EXTERN_MEM_INT (7 + PRIMARY_INTS) -+#define AVALANCHE_DSP_A_DOG (8 + PRIMARY_INTS) -+#define AVALANCHE_DSP_B_DOG (9 + PRIMARY_INTS) -+/* Line #10-#20 Reserved */ -+#define AVALANCHE_ETH_MACB_LNK_CHG (21 + PRIMARY_INTS) -+#define AVALANCHE_ETH_MACB_MGT (22 + PRIMARY_INTS) -+#define AVALANCHE_AAL2_STATUS (23 + PRIMARY_INTS) -+/* Line #24-#31 Reserved */ -+ -+#define AVALANCHEINT_UART0 LNXINTNUM(AVALANCHE_UART0_INT) -+#define AVALANCHEINT_UART1 LNXINTNUM(AVALANCHE_UART1_INT) -+#define SEADINT_UART0 3 /* TTYS0 interrupt on SEAD */ -+#define SEADINT_UART1 4 /* TTYS1 interrupt on SEAD */ -+ -+#ifdef JIMK_INT_CTRLR -+/*-----------------------------------*/ -+/* Jim Kennedy's Interrupt Controller*/ -+/*-----------------------------------*/ ++void avalanche_power_ctrl(unsigned int power_module, AVALANCHE_POWER_CTRL_T power_ctrl); ++AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int power_module); ++void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode); ++AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void); + -+/* to clear the interrupt write the bit back to the status reg */ ++/***************************************************************************** ++ * Wakeup Control ++ *****************************************************************************/ + -+#define JIMK_INT_STATUS (*(volatile unsigned int *)(0xA8612400)) -+#define JIMK_INT_MASK (*(volatile unsigned int *)(0xA8612404)) -+#define JIMK_SAR_STATUS (1<<0) -+#define JIMK_SAR_TX_A (1<<1) -+#define JIMK_SAR_TX_B (1<<2) -+#define JIMK_SAR_RX_A (1<<3) -+#define JIMK_SAR_RX_B (1<<4) -+#define JIMK_AAL2_STATUS (1<<5) -+#define JIMK_UART0_INT (1<<11) ++typedef enum AVALANCHE_WAKEUP_INTERRUPT_tag ++{ ++ WAKEUP_INT0 = 1, ++ WAKEUP_INT1 = 2, ++ WAKEUP_INT2 = 4, ++ WAKEUP_INT3 = 8 ++} AVALANCHE_WAKEUP_INTERRUPT_T; + -+#ifdef SEAD_USB_DEVELOPMENT -+#define JIMK_USB_INT (1<<0) -+#endif /* SEAD_USB_DEVELOPMENT */ ++typedef enum TNETV1050_WAKEUP_CTRL_tag ++{ ++ WAKEUP_DISABLED = 0, ++ WAKEUP_ENABLED ++} AVALANCHE_WAKEUP_CTRL_T; + -+#endif /* JIMK_INT_CTRLR */ ++typedef enum TNETV1050_WAKEUP_POLARITY_tag ++{ ++ WAKEUP_ACTIVE_HIGH = 0, ++ WAKEUP_ACTIVE_LOW ++} AVALANCHE_WAKEUP_POLARITY_T; + -+extern void avalanche_int_set(int channel, int line); -+extern void avalancheint_init(void); ++void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int, ++ AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl, ++ AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity); + ++/***************************************************************************** ++ * GPIO Control ++ *****************************************************************************/ + -+#endif /* !(_MIPS_AVALANCHEINT_H) */ ++typedef enum AVALANCHE_GPIO_PIN_MODE_tag ++{ ++ FUNCTIONAL_PIN = 0, ++ GPIO_PIN = 1 ++} AVALANCHE_GPIO_PIN_MODE_T; + ++typedef enum AVALANCHE_GPIO_PIN_DIRECTION_tag ++{ ++ GPIO_OUTPUT_PIN = 0, ++ GPIO_INPUT_PIN = 1 ++} AVALANCHE_GPIO_PIN_DIRECTION_T; + ++typedef enum { GPIO_FALSE, GPIO_TRUE } AVALANCHE_GPIO_BOOL_T; + ++void avalanche_gpio_init(void); ++int avalanche_gpio_ctrl(unsigned int gpio_pin, ++ AVALANCHE_GPIO_PIN_MODE_T pin_mode, ++ AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction); ++int avalanche_gpio_ctrl_with_link_count(unsigned int gpio_pin, ++ AVALANCHE_GPIO_PIN_MODE_T pin_mode, ++ AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction); ++int avalanche_gpio_out_bit(unsigned int gpio_pin, int value); ++int avalanche_gpio_in_bit(unsigned int gpio_pin); ++int avalanche_gpio_out_value(unsigned int out_val, unsigned int set_mask, unsigned int reg_index); ++int avalanche_gpio_out_value_with_link_count(unsigned int out_val, unsigned int set_mask, unsigned int reg_index); ++int avalanche_gpio_in_value(unsigned int *in_val, unsigned int reg_index); + -diff -urN linux.old/include/asm-mips/ar7/avalanche_prom.h linux.dev/include/asm-mips/ar7/avalanche_prom.h ---- linux.old/include/asm-mips/ar7/avalanche_prom.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/ar7/avalanche_prom.h 2005-07-07 04:39:14.431224000 +0200 -@@ -0,0 +1,54 @@ -+/* $Id$ -+ * -+ * prom.h -+ * -+ * Carsten Langgaard, carstenl@mips.com -+ * Copyright (C) 1999 MIPS Technologies, Inc. -+ * -+ * ######################################################################## -+ * -+ * This program is free software; you can distribute it and/or modify it -+ * under the terms of the GNU General Public License (Version 2) as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * for more details. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -+ * -+ * ######################################################################## -+ * -+ * Sead bootprom interface for the Linux kernel. -+ * -+ */ ++unsigned int avalanche_get_chip_version_info(void); + -+#ifndef _MIPS_PROM_H -+#define _MIPS_PROM_H -+ -+extern char *prom_getcmdline(void); -+extern char *prom_getenv(char *name); -+extern void setup_prom_printf(void); -+extern void prom_printf(char *fmt, ...); -+extern void prom_init_cmdline(void); -+extern void prom_meminit(void); -+extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem); -+extern void prom_free_prom_memory (void); -+extern void sead_display_message(const char *str); -+extern void sead_display_word(unsigned int num); -+extern int get_ethernet_addr(char *ethernet_addr); -+ -+/* Memory descriptor management. */ -+#define PROM_MAX_PMEMBLOCKS 32 -+struct prom_pmemblock { -+ unsigned long base; /* Within KSEG0. */ -+ unsigned int size; /* In bytes. */ -+ unsigned int type; /* free or prom memory */ -+}; ++unsigned int avalanche_get_vbus_freq(void); ++void avalanche_set_vbus_freq(unsigned int); + + -+#endif /* !(_MIPS_PROM_H) */ ++typedef int (*SET_MDIX_ON_CHIP_FN_T)(unsigned int base_addr, unsigned int operation); ++int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation); ++unsigned int avalanche_is_mdix_on_chip(void); + -diff -urN linux.old/include/asm-mips/ar7/avalanche_regs.h linux.dev/include/asm-mips/ar7/avalanche_regs.h ---- linux.old/include/asm-mips/ar7/avalanche_regs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/ar7/avalanche_regs.h 2005-07-07 04:39:14.433224000 +0200 ++#endif +diff -urN kernel-base/include/asm-mips/ar7/avalanche_regs.h kernel-current/include/asm-mips/ar7/avalanche_regs.h +--- kernel-base/include/asm-mips/ar7/avalanche_regs.h 1970-01-01 01:00:00.000000000 +0100 ++++ kernel-current/include/asm-mips/ar7/avalanche_regs.h 2005-07-10 18:48:26.333254256 +0200 @@ -0,0 +1,567 @@ +/* + * $Id$ @@ -4935,653 +3936,311 @@ diff -urN linux.old/include/asm-mips/ar7/avalanche_regs.h linux.dev/include/asm- + +#define VMAC_STATS_BASE(X) (X + 0x00000400) + -+#endif -+ -+ -+ -+ -+ -+ -diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_err.h linux.dev/include/asm-mips/ar7/tnetd73xx_err.h ---- linux.old/include/asm-mips/ar7/tnetd73xx_err.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/ar7/tnetd73xx_err.h 2005-07-07 04:39:14.434224000 +0200 -@@ -0,0 +1,42 @@ -+/****************************************************************************** -+ * FILE PURPOSE: TNETD73xx Error Definations Header File -+ ****************************************************************************** -+ * FILE NAME: tnetd73xx_err.h -+ * -+ * DESCRIPTION: Error definations for TNETD73XX -+ * -+ * REVISION HISTORY: -+ * 27 Nov 02 - PSP TII -+ * -+ * (C) Copyright 2002, Texas Instruments, Inc -+ *******************************************************************************/ -+ -+ -+#ifndef __TNETD73XX_ERR_H__ -+#define __TNETD73XX_ERR_H__ -+ -+typedef enum TNETD73XX_ERR_t -+{ -+ TNETD73XX_ERR_OK = 0, /* OK or SUCCESS */ -+ TNETD73XX_ERR_ERROR = -1, /* Unspecified/Generic ERROR */ -+ -+ /* Pointers and args */ -+ TNETD73XX_ERR_INVARG = -2, /* Invaild argument to the call */ -+ TNETD73XX_ERR_NULLPTR = -3, /* NULL pointer */ -+ TNETD73XX_ERR_BADPTR = -4, /* Bad (out of mem) pointer */ -+ -+ /* Memory issues */ -+ TNETD73XX_ERR_ALLOC_FAIL = -10, /* allocation failed */ -+ TNETD73XX_ERR_FREE_FAIL = -11, /* free failed */ -+ TNETD73XX_ERR_MEM_CORRUPT = -12, /* corrupted memory */ -+ TNETD73XX_ERR_BUF_LINK = -13, /* buffer linking failed */ -+ -+ /* Device issues */ -+ TNETD73XX_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */ -+ TNETD73XX_ERR_DEVICE_MALFUNC = -21, /* device malfunction */ ++#endif __AVALANCHE_REGS_H + -+ TNETD73XX_ERR_INVID = -30 /* Invalid ID */ + -+} TNETD73XX_ERR; + -+#endif /* __TNETD73XX_ERR_H__ */ -diff -urN linux.old/include/asm-mips/ar7/tnetd73xx.h linux.dev/include/asm-mips/ar7/tnetd73xx.h ---- linux.old/include/asm-mips/ar7/tnetd73xx.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/ar7/tnetd73xx.h 2005-07-07 04:39:14.433224000 +0200 -@@ -0,0 +1,340 @@ -+/****************************************************************************** -+ * FILE PURPOSE: TNETD73xx Common Header File -+ ****************************************************************************** -+ * FILE NAME: tnetd73xx.h -+ * -+ * DESCRIPTION: shared typedef's, constants and API for TNETD73xx -+ * -+ * REVISION HISTORY: -+ * 27 Nov 02 - PSP TII -+ * -+ * (C) Copyright 2002, Texas Instruments, Inc -+ *******************************************************************************/ + -+/* -+ * -+ * -+ * These are const, typedef, and api definitions for tnetd73xx. -+ * -+ * NOTES: -+ * 1. This file may be included into both C and Assembly files. -+ * - for .s files, please do #define _ASMLANGUAGE in your ASM file to -+ * avoid C data types (typedefs) below; -+ * - for .c files, you don't have to do anything special. -+ * -+ * 2. This file has a number of sections for each SOC subsystem. When adding -+ * a new constant, find the subsystem you are working on and follow the -+ * name pattern. If you are adding another typedef for your interface, please, -+ * place it with other typedefs and function prototypes. -+ * -+ * 3. Please, DO NOT add any macros or types that are local to a subsystem to avoid -+ * cluttering. Include such items directly into the module's .c file or have a -+ * local .h file to pass data between smaller modules. This file defines only -+ * shared items. -+ */ + -+#ifndef __TNETD73XX_H__ -+#define __TNETD73XX_H__ + -+#ifndef _ASMLANGUAGE /* This part not for assembly language */ +diff -urN kernel-base/include/asm-mips/ar7/if_port.h kernel-current/include/asm-mips/ar7/if_port.h +--- kernel-base/include/asm-mips/ar7/if_port.h 1970-01-01 01:00:00.000000000 +0100 ++++ kernel-current/include/asm-mips/ar7/if_port.h 2005-07-10 06:40:39.623260000 +0200 +@@ -0,0 +1,26 @@ ++/******************************************************************************* ++ * FILE PURPOSE: Interface port id Header file ++ ******************************************************************************* ++ * FILE NAME: if_port.h ++ * ++ * DESCRIPTION: Header file carrying information about port ids of interfaces ++ * ++ * ++ * (C) Copyright 2003, Texas Instruments, Inc ++ ******************************************************************************/ ++#ifndef _IF_PORT_H_ ++#define _IF_PORT_H_ + -+#include ++#define AVALANCHE_CPMAC_LOW_PORT_ID 0 ++#define AVALANCHE_CPMAC_HIGH_PORT_ID 1 ++#define AVALANCHE_USB_PORT_ID 2 ++#define AVALANCHE_WLAN_PORT_ID 3 + -+extern unsigned int tnetd73xx_mips_freq; -+extern unsigned int tnetd73xx_vbus_freq; + -+#include "tnetd73xx_err.h" ++#define AVALANCHE_MARVELL_BASE_PORT_ID 4 + -+#endif /* _ASMLANGUAGE */ ++/* The marvell ports occupy port ids from 4 to 8 */ ++/* so the next port id number should start at 9 */ + + -+/******************************************************************************************* -+* Emerald core specific -+******************************************************************************************** */ ++#endif /* _IF_PORT_H_ */ +diff -urN kernel-base/include/asm-mips/ar7/sangam_boards.h kernel-current/include/asm-mips/ar7/sangam_boards.h +--- kernel-base/include/asm-mips/ar7/sangam_boards.h 1970-01-01 01:00:00.000000000 +0100 ++++ kernel-current/include/asm-mips/ar7/sangam_boards.h 2005-07-10 06:40:39.623260000 +0200 +@@ -0,0 +1,77 @@ ++#ifndef _SANGAM_BOARDS_H ++#define _SANGAM_BOARDS_H + -+#ifdef BIG_ENDIAN -+#elif defined(LITTLE_ENDIAN) -+#else -+#error Need to define endianism -+#endif ++// Let us define board specific information here. + -+#ifndef KSEG_MSK -+#define KSEG_MSK 0xE0000000 /* Most significant 3 bits denote kseg choice */ -+#endif + -+#ifndef KSEG_INV_MASK -+#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */ -+#endif ++#if defined(CONFIG_AR7DB) + -+#ifndef KSEG0_BASE -+#define KSEG0_BASE 0x80000000 -+#endif ++#define AFECLK_FREQ 35328000 ++#define REFCLK_FREQ 25000000 ++#define OSC3_FREQ 24000000 ++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000 ++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555 ++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000 + -+#ifndef KSEG1_BASE -+#define KSEG1_BASE 0xA0000000 +#endif + -+#ifndef KSEG0 -+#define KSEG0(addr) (((u32)(addr) & ~KSEG_MSK) | KSEG0_BASE) -+#endif + -+#ifndef KSEG1 -+#define KSEG1(addr) (((u32)(addr) & ~KSEG_MSK) | KSEG1_BASE) ++#if defined(CONFIG_AR7RD) ++#define AFECLK_FREQ 35328000 ++#define REFCLK_FREQ 25000000 ++#define OSC3_FREQ 24000000 ++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000 ++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2 ++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000 +#endif + -+#ifndef KUSEG -+#define KUSEG(addr) ((u32)(addr) & ~KSEG_MSK) -+#endif + -+#ifndef PHYS_ADDR -+#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK) ++#if defined(CONFIG_AR7WI) ++#define AFECLK_FREQ 35328000 ++#define REFCLK_FREQ 25000000 ++#define OSC3_FREQ 24000000 ++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000 ++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2 ++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000 +#endif + -+#ifndef PHYS_TO_K0 -+#define PHYS_TO_K0(addr) (PHYS_ADDR(addr)|KSEG0_BASE) -+#endif + -+#ifndef PHYS_TO_K1 -+#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE) ++#if defined(CONFIG_AR7V) ++#define AFECLK_FREQ 35328000 ++#define REFCLK_FREQ 25000000 ++#define OSC3_FREQ 24000000 ++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000 ++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2 ++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000 +#endif + -+#ifndef REG8_ADDR -+#define REG8_ADDR(addr) (volatile u8 *)(PHYS_TO_K1(addr)) -+#define REG8_DATA(addr) (*(volatile u8 *)(PHYS_TO_K1(addr))) -+#define REG8_WRITE(addr, data) REG8_DATA(addr) = data; -+#define REG8_READ(addr, data) data = (u8) REG8_DATA(addr); -+#endif + -+#ifndef REG16_ADDR -+#define REG16_ADDR(addr) (volatile u16 *)(PHYS_TO_K1(addr)) -+#define REG16_DATA(addr) (*(volatile u16 *)(PHYS_TO_K1(addr))) -+#define REG16_WRITE(addr, data) REG16_DATA(addr) = data; -+#define REG16_READ(addr, data) data = (u16) REG16_DATA(addr); ++#if defined(CONFIG_AR7WRD) ++#define AFECLK_FREQ 35328000 ++#define REFCLK_FREQ 25000000 ++#define OSC3_FREQ 24000000 ++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000 ++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000 ++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000 +#endif + -+#ifndef REG32_ADDR -+#define REG32_ADDR(addr) (volatile u32 *)(PHYS_TO_K1(addr)) -+#define REG32_DATA(addr) (*(volatile u32 *)(PHYS_TO_K1(addr))) -+#define REG32_WRITE(addr, data) REG32_DATA(addr) = data; -+#define REG32_READ(addr, data) data = (u32) REG32_DATA(addr); -+#endif + -+#ifdef _LINK_KSEG0_ /* Application is linked into KSEG0 space */ -+#define VIRT_ADDR(addr) PHYS_TO_K0(PHYS_ADDR(addr)) ++#if defined(CONFIG_AR7VWI) ++#define AFECLK_FREQ 35328000 ++#define REFCLK_FREQ 25000000 ++#define OSC3_FREQ 24000000 ++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000 ++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000 ++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000 +#endif + -+#ifdef _LINK_KSEG1_ /* Application is linked into KSEG1 space */ -+#define VIRT_ADDR(addr) PHYS_TO_K1(PHYS_ADDR(addr)) -+#endif + -+#if !defined(_LINK_KSEG0_) && !defined(_LINK_KSEG1_) -+#error You must define _LINK_KSEG0_ or _LINK_KSEG1_ to compile the code. ++#if defined CONFIG_SEAD2 ++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0xAAAAAAAA ++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555 ++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0 ++#include +#endif + -+/* TNETD73XX chip definations */ -+ -+#define FREQ_1MHZ 1000000 -+#define TNETD73XX_MIPS_FREQ tnetd73xx_mips_freq /* CPU clock frequency */ -+#define TNETD73XX_VBUS_FREQ tnetd73xx_vbus_freq /* originally (TNETD73XX_MIPS_FREQ/2) */ + -+#ifdef AR7SEAD2 -+#define TNETD73XX_MIPS_FREQ_DEFAULT 25000000 /* 25 Mhz for sead2 board crystal */ -+#else -+#define TNETD73XX_MIPS_FREQ_DEFAULT 125000000 /* 125 Mhz */ -+#endif -+#define TNETD73XX_VBUS_FREQ_DEFAULT (TNETD73XX_MIPS_FREQ_DEFAULT / 2) /* Sync mode */ -+ -+ -+ -+/* Module base addresses */ -+#define TNETD73XX_ADSLSS_BASE PHYS_TO_K1(0x01000000) /* ADSLSS Module */ -+#define TNETD73XX_BBIF_CTRL_BASE PHYS_TO_K1(0x02000000) /* BBIF Control */ -+#define TNETD73XX_ATMSAR_BASE PHYS_TO_K1(0x03000000) /* ATM SAR */ -+#define TNETD73XX_USB_BASE PHYS_TO_K1(0x03400000) /* USB Module */ -+#define TNETD73XX_VLYNQ0_BASE PHYS_TO_K1(0x04000000) /* VLYNQ0 Module */ -+#define TNETD73xx_EMAC0_BASE PHYS_TO_K1(0x08610000) /* EMAC0 Module*/ -+#define TNETD73XX_EMIF_BASE PHYS_TO_K1(0x08610800) /* EMIF Module */ -+#define TNETD73XX_GPIO_BASE PHYS_TO_K1(0x08610900) /* GPIO control */ -+#define TNETD73XX_CLOCK_CTRL_BASE PHYS_TO_K1(0x08610A00) /* Clock Control */ -+#define TNETD73XX_WDTIMER_BASE PHYS_TO_K1(0x08610B00) /* WDTIMER Module */ -+#define TNETD73XX_TIMER0_BASE PHYS_TO_K1(0x08610C00) /* TIMER0 Module */ -+#define TNETD73XX_TIMER1_BASE PHYS_TO_K1(0x08610D00) /* TIMER1 Module */ -+#define TNETD73XX_UARTA_BASE PHYS_TO_K1(0x08610E00) /* UART A */ -+#define TNETD73XX_UARTB_BASE PHYS_TO_K1(0x08610F00) /* UART B */ -+#define TNETD73XX_I2C_BASE PHYS_TO_K1(0x08611000) /* I2C Module */ -+#define TNETD73XX_USB_DMA_BASE PHYS_TO_K1(0x08611200) /* USB Module */ -+#define TNETD73XX_MCDMA_BASE PHYS_TO_K1(0x08611400) /* MC-DMA */ -+#define TNETD73xx_VDMAVT_BASE PHYS_TO_K1(0x08611500) /* VDMAVT Control */ -+#define TNETD73XX_RST_CTRL_BASE PHYS_TO_K1(0x08611600) /* Reset Control */ -+#define TNETD73xx_BIST_CTRL_BASE PHYS_TO_K1(0x08611700) /* BIST Control */ -+#define TNETD73xx_VLYNQ0_CTRL_BASE PHYS_TO_K1(0x08611800) /* VLYNQ0 Control */ -+#define TNETD73XX_DCL_BASE PHYS_TO_K1(0x08611A00) /* Device Configuration Latch */ -+#define TNETD73xx_VLYNQ1_CTRL_BASE PHYS_TO_K1(0x08611C00) /* VLYNQ1 Control */ -+#define TNETD73xx_MDIO_BASE PHYS_TO_K1(0x08611E00) /* MDIO Control */ -+#define TNETD73XX_FSER_BASE PHYS_TO_K1(0x08612000) /* FSER Control */ -+#define TNETD73XX_INTC_BASE PHYS_TO_K1(0x08612400) /* Interrupt Controller */ -+#define TNETD73xx_EMAC1_BASE PHYS_TO_K1(0x08612800) /* EMAC1 Module*/ -+#define TNETD73XX_VLYNQ1_BASE PHYS_TO_K1(0x0C000000) /* VLYNQ1 Module */ -+ -+/* BBIF Registers */ -+#define TNETD73XX_BBIF_ADSLADR (TNETD73XX_BBIF_CTRL_BASE + 0x0) -+ -+/* Device Configuration Latch Registers */ -+#define TNETD73XX_DCL_BOOTCR (TNETD73XX_DCL_BASE + 0x0) -+#define TNETD73XX_DCL_DPLLSELR (TNETD73XX_DCL_BASE + 0x10) -+#define TNETD73XX_DCL_SPEEDCTLR (TNETD73XX_DCL_BASE + 0x14) -+#define TNETD73XX_DCL_SPEEDPWDR (TNETD73XX_DCL_BASE + 0x18) -+#define TNETD73XX_DCL_SPEEDCAPR (TNETD73XX_DCL_BASE + 0x1C) -+ -+/* GPIO Control */ -+#define TNETD73XX_GPIODINR (TNETD73XX_GPIO_BASE + 0x0) -+#define TNETD73XX_GPIODOUTR (TNETD73XX_GPIO_BASE + 0x4) -+#define TNETD73XX_GPIOPDIRR (TNETD73XX_GPIO_BASE + 0x8) -+#define TNETD73XX_GPIOENR (TNETD73XX_GPIO_BASE + 0xC) -+#define TNETD73XX_CVR (TNETD73XX_GPIO_BASE + 0x14) -+#define TNETD73XX_DIDR1 (TNETD73XX_GPIO_BASE + 0x18) -+#define TNETD73XX_DIDR2 (TNETD73XX_GPIO_BASE + 0x1C) -+ -+/* Reset Control */ -+#define TNETD73XX_RST_CTRL_PRCR (TNETD73XX_RST_CTRL_BASE + 0x0) -+#define TNETD73XX_RST_CTRL_SWRCR (TNETD73XX_RST_CTRL_BASE + 0x4) -+#define TNETD73XX_RST_CTRL_RSR (TNETD73XX_RST_CTRL_BASE + 0x8) -+ -+/* Power Control */ -+#define TNETD73XX_POWER_CTRL_PDCR (TNETD73XX_CLOCK_CTRL_BASE + 0x0) -+#define TNETD73XX_POWER_CTRL_PCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x4) -+#define TNETD73XX_POWER_CTRL_PDUCR (TNETD73XX_CLOCK_CTRL_BASE + 0x8) -+#define TNETD73XX_POWER_CTRL_WKCR (TNETD73XX_CLOCK_CTRL_BASE + 0xC) -+ -+/* Clock Control */ -+#define TNETD73XX_CLK_CTRL_SCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x20) -+#define TNETD73XX_CLK_CTRL_SCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x30) -+#define TNETD73XX_CLK_CTRL_MCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x40) -+#define TNETD73XX_CLK_CTRL_MCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x50) -+#define TNETD73XX_CLK_CTRL_UCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x60) -+#define TNETD73XX_CLK_CTRL_UCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x70) -+#define TNETD73XX_CLK_CTRL_ACLKCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x80) -+#define TNETD73XX_CLK_CTRL_ACLKPLLCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x90) -+#define TNETD73XX_CLK_CTRL_ACLKCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xA0) -+#define TNETD73XX_CLK_CTRL_ACLKPLLCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xB0) -+ -+/* EMIF control */ -+#define TNETD73XX_EMIF_SDRAM_CFG ( TNETD73XX_EMIF_BASE + 0x08 ) -+ -+/* UART */ -+#ifdef AR7SEAD2 -+#define TNETD73XX_UART_FREQ 3686400 -+#else -+#define TNETD73XX_UART_FREQ TNETD73XX_VBUS_FREQ +#endif +diff -urN kernel-base/include/asm-mips/ar7/sangam.h kernel-current/include/asm-mips/ar7/sangam.h +--- kernel-base/include/asm-mips/ar7/sangam.h 1970-01-01 01:00:00.000000000 +0100 ++++ kernel-current/include/asm-mips/ar7/sangam.h 2005-07-10 06:40:39.624260000 +0200 +@@ -0,0 +1,180 @@ ++#ifndef _SANGAM_H_ ++#define _SANGAM_H_ + -+/* Interrupt Controller */ -+ -+/* Primary interrupts */ -+#define TNETD73XX_INTC_UNIFIED_SECONDARY 0 /* Unified secondary interrupt */ -+#define TNETD73XX_INTC_EXTERNAL0 1 /* External Interrupt Line 0 */ -+#define TNETD73XX_INTC_EXTERNAL1 2 /* External Interrupt Line 1 */ -+#define TNETD73XX_INTC_RESERVED3 3 /* Reserved */ -+#define TNETD73XX_INTC_RESERVED4 4 /* Reserved */ -+#define TNETD73XX_INTC_TIMER0 5 /* TIMER 0 int */ -+#define TNETD73XX_INTC_TIMER1 6 /* TIMER 1 int */ -+#define TNETD73XX_INTC_UART0 7 /* UART 0 int */ -+#define TNETD73XX_INTC_UART1 8 /* UART 1 int */ -+#define TNETD73XX_INTC_MCDMA0 9 /* MCDMA 0 int */ -+#define TNETD73XX_INTC_MCDMA1 10 /* MCDMA 1 int */ -+#define TNETD73XX_INTC_RESERVED11 11 /* Reserved */ -+#define TNETD73XX_INTC_RESERVED12 12 /* Reserved */ -+#define TNETD73XX_INTC_RESERVED13 13 /* Reserved */ -+#define TNETD73XX_INTC_RESERVED14 14 /* Reserved */ -+#define TNETD73XX_INTC_ATMSAR 15 /* ATM SAR int */ -+#define TNETD73XX_INTC_RESERVED16 16 /* Reserved */ -+#define TNETD73XX_INTC_RESERVED17 17 /* Reserved */ -+#define TNETD73XX_INTC_RESERVED18 18 /* Reserved */ -+#define TNETD73XX_INTC_EMAC0 19 /* EMAC 0 int */ -+#define TNETD73XX_INTC_RESERVED20 20 /* Reserved */ -+#define TNETD73XX_INTC_VLYNQ0 21 /* VLYNQ 0 int */ -+#define TNETD73XX_INTC_CODEC 22 /* CODEC int */ -+#define TNETD73XX_INTC_RESERVED23 23 /* Reserved */ -+#define TNETD73XX_INTC_USBSLAVE 24 /* USB Slave int */ -+#define TNETD73XX_INTC_VLYNQ1 25 /* VLYNQ 1 int */ -+#define TNETD73XX_INTC_RESERVED26 26 /* Reserved */ -+#define TNETD73XX_INTC_RESERVED27 27 /* Reserved */ -+#define TNETD73XX_INTC_ETH_PHY 28 /* Ethernet PHY */ -+#define TNETD73XX_INTC_I2C 29 /* I2C int */ -+#define TNETD73XX_INTC_MCDMA2 30 /* MCDMA 2 int */ -+#define TNETD73XX_INTC_MCDMA3 31 /* MCDMA 3 int */ -+#define TNETD73XX_INTC_RESERVED32 32 /* Reserved */ -+#define TNETD73XX_INTC_EMAC1 33 /* EMAC 1 int */ -+#define TNETD73XX_INTC_RESERVED34 34 /* Reserved */ -+#define TNETD73XX_INTC_RESERVED35 35 /* Reserved */ -+#define TNETD73XX_INTC_RESERVED36 36 /* Reserved */ -+#define TNETD73XX_INTC_VDMAVTRX 37 /* VDMAVTRX */ -+#define TNETD73XX_INTC_VDMAVTTX 38 /* VDMAVTTX */ -+#define TNETD73XX_INTC_ADSLSS 39 /* ADSLSS */ -+ -+/* Secondary interrupts */ -+#define TNETD73XX_INTC_SEC0 40 /* Secondary */ -+#define TNETD73XX_INTC_SEC1 41 /* Secondary */ -+#define TNETD73XX_INTC_SEC2 42 /* Secondary */ -+#define TNETD73XX_INTC_SEC3 43 /* Secondary */ -+#define TNETD73XX_INTC_SEC4 44 /* Secondary */ -+#define TNETD73XX_INTC_SEC5 45 /* Secondary */ -+#define TNETD73XX_INTC_SEC6 46 /* Secondary */ -+#define TNETD73XX_INTC_EMIF 47 /* EMIF */ -+#define TNETD73XX_INTC_SEC8 48 /* Secondary */ -+#define TNETD73XX_INTC_SEC9 49 /* Secondary */ -+#define TNETD73XX_INTC_SEC10 50 /* Secondary */ -+#define TNETD73XX_INTC_SEC11 51 /* Secondary */ -+#define TNETD73XX_INTC_SEC12 52 /* Secondary */ -+#define TNETD73XX_INTC_SEC13 53 /* Secondary */ -+#define TNETD73XX_INTC_SEC14 54 /* Secondary */ -+#define TNETD73XX_INTC_SEC15 55 /* Secondary */ -+#define TNETD73XX_INTC_SEC16 56 /* Secondary */ -+#define TNETD73XX_INTC_SEC17 57 /* Secondary */ -+#define TNETD73XX_INTC_SEC18 58 /* Secondary */ -+#define TNETD73XX_INTC_SEC19 59 /* Secondary */ -+#define TNETD73XX_INTC_SEC20 60 /* Secondary */ -+#define TNETD73XX_INTC_SEC21 61 /* Secondary */ -+#define TNETD73XX_INTC_SEC22 62 /* Secondary */ -+#define TNETD73XX_INTC_SEC23 63 /* Secondary */ -+#define TNETD73XX_INTC_SEC24 64 /* Secondary */ -+#define TNETD73XX_INTC_SEC25 65 /* Secondary */ -+#define TNETD73XX_INTC_SEC26 66 /* Secondary */ -+#define TNETD73XX_INTC_SEC27 67 /* Secondary */ -+#define TNETD73XX_INTC_SEC28 68 /* Secondary */ -+#define TNETD73XX_INTC_SEC29 69 /* Secondary */ -+#define TNETD73XX_INTC_SEC30 70 /* Secondary */ -+#define TNETD73XX_INTC_SEC31 71 /* Secondary */ -+ -+/* These ugly macros are to access the -1 registers, like config1 */ -+#define MFC0_SEL1_OPCODE(dst, src)\ -+ .word (0x40000000 | ((dst)<<16) | ((src)<<11) | 1);\ -+ nop; \ -+ nop; \ -+ nop -+ -+#define MTC0_SEL1_OPCODE(dst, src)\ -+ .word (0x40800000 | ((dst)<<16) | ((src)<<11) | 1);\ -+ nop; \ -+ nop; \ -+ nop -+ -+ -+/* Below are Jade core specific */ -+#define CFG0_4K_IL_MASK 0x00380000 -+#define CFG0_4K_IL_SHIFT 19 -+#define CFG0_4K_IA_MASK 0x00070000 -+#define CFG0_4K_IA_SHIFT 16 -+#define CFG0_4K_IS_MASK 0x01c00000 -+#define CFG0_4K_IS_SHIFT 22 -+ -+#define CFG0_4K_DL_MASK 0x00001c00 -+#define CFG0_4K_DL_SHIFT 10 -+#define CFG0_4K_DA_MASK 0x00000380 -+#define CFG0_4K_DA_SHIFT 7 -+#define CFG0_4K_DS_MASK 0x0000E000 -+#define CFG0_4K_DS_SHIFT 13 -+ -+ -+ -+#endif /* __TNETD73XX_H_ */ -diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_misc.h linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h ---- linux.old/include/asm-mips/ar7/tnetd73xx_misc.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h 2005-07-07 04:39:14.434224000 +0200 -@@ -0,0 +1,243 @@ -+/****************************************************************************** -+ * FILE PURPOSE: TNETD73xx Misc modules API Header -+ ****************************************************************************** -+ * FILE NAME: tnetd73xx_misc.h -+ * -+ * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO -+ * FSER Modules API -+ * As per TNETD73xx specifications -+ * -+ * REVISION HISTORY: -+ * 27 Nov 02 - Sharath Kumar PSP TII -+ * 14 Feb 03 - Anant Gole PSP TII -+ * -+ * (C) Copyright 2002, Texas Instruments, Inc -+ *******************************************************************************/ -+ -+#ifndef __TNETD73XX_MISC_H__ -+#define __TNETD73XX_MISC_H__ -+ -+#include -+ -+#define BOOTCR_MIPS_ASYNC_MODE (1 << 25) -+ -+/***************************************************************************** -+ * Reset Control Module -+ *****************************************************************************/ -+ -+typedef enum TNETD73XX_RESET_MODULE_tag -+{ -+ RESET_MODULE_UART0 = 0, -+ RESET_MODULE_UART1 = 1, -+ RESET_MODULE_I2C = 2, -+ RESET_MODULE_TIMER0 = 3, -+ RESET_MODULE_TIMER1 = 4, -+ RESET_MODULE_GPIO = 6, -+ RESET_MODULE_ADSLSS = 7, -+ RESET_MODULE_USBS = 8, -+ RESET_MODULE_SAR = 9, -+ RESET_MODULE_VDMA_VT = 11, -+ RESET_MODULE_FSER = 12, -+ RESET_MODULE_VLYNQ1 = 16, -+ RESET_MODULE_EMAC0 = 17, -+ RESET_MODULE_DMA = 18, -+ RESET_MODULE_BIST = 19, -+ RESET_MODULE_VLYNQ0 = 20, -+ RESET_MODULE_EMAC1 = 21, -+ RESET_MODULE_MDIO = 22, -+ RESET_MODULE_ADSLSS_DSP = 23, -+ RESET_MODULE_EPHY = 26 -+} TNETD73XX_RESET_MODULE_T; -+ -+typedef enum TNETD73XX_RESET_CTRL_tag -+{ -+ IN_RESET = 0, -+ OUT_OF_RESET -+} TNETD73XX_RESET_CTRL_T; -+ -+typedef enum TNETD73XX_SYS_RST_MODE_tag -+{ -+ RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */ -+ RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */ -+} TNETD73XX_SYS_RST_MODE_T; -+ -+typedef enum TNETD73XX_SYS_RESET_STATUS_tag -+{ -+ HARDWARE_RESET = 0, -+ SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */ -+ WATCHDOG_RESET, -+ SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */ -+} TNETD73XX_SYS_RESET_STATUS_T; -+ -+void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, -+ TNETD73XX_RESET_CTRL_T reset_ctrl); -+TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status(TNETD73XX_RESET_MODULE_T reset_module); -+void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode); -+TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status(void); -+ -+/***************************************************************************** -+ * Power Control Module -+ *****************************************************************************/ -+ -+typedef enum TNETD73XX_POWER_MODULE_tag -+{ -+ POWER_MODULE_USBSP = 0, -+ POWER_MODULE_WDTP = 1, -+ POWER_MODULE_UT0P = 2, -+ POWER_MODULE_UT1P = 3, -+ POWER_MODULE_IICP = 4, -+ POWER_MODULE_VDMAP = 5, -+ POWER_MODULE_GPIOP = 6, -+ POWER_MODULE_VLYNQ1P = 7, -+ POWER_MODULE_SARP = 8, -+ POWER_MODULE_ADSLP = 9, -+ POWER_MODULE_EMIFP = 10, -+ POWER_MODULE_ADSPP = 12, -+ POWER_MODULE_RAMP = 13, -+ POWER_MODULE_ROMP = 14, -+ POWER_MODULE_DMAP = 15, -+ POWER_MODULE_BISTP = 16, -+ POWER_MODULE_TIMER0P = 18, -+ POWER_MODULE_TIMER1P = 19, -+ POWER_MODULE_EMAC0P = 20, -+ POWER_MODULE_EMAC1P = 22, -+ POWER_MODULE_EPHYP = 24, -+ POWER_MODULE_VLYNQ0P = 27, -+} TNETD73XX_POWER_MODULE_T; -+ -+typedef enum TNETD73XX_POWER_CTRL_tag -+{ -+ POWER_CTRL_POWER_UP = 0, -+ POWER_CTRL_POWER_DOWN -+} TNETD73XX_POWER_CTRL_T; -+ -+typedef enum TNETD73XX_SYS_POWER_MODE_tag -+{ -+ GLOBAL_POWER_MODE_RUN = 0, /* All system is up */ -+ GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */ -+ GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */ -+ GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */ -+} TNETD73XX_SYS_POWER_MODE_T; -+ -+void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl); -+TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module); -+void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode); -+TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode(void); -+ -+/***************************************************************************** -+ * Wakeup Control -+ *****************************************************************************/ ++#include ++#include + -+typedef enum TNETD73XX_WAKEUP_INTERRUPT_tag -+{ -+ WAKEUP_INT0 = 1, -+ WAKEUP_INT1 = 2, -+ WAKEUP_INT2 = 4, -+ WAKEUP_INT3 = 8 -+} TNETD73XX_WAKEUP_INTERRUPT_T; ++/*---------------------------------------------------- ++ * Sangam's Module Base Addresses ++ *--------------------------------------------------*/ ++#define AVALANCHE_ADSL_SUB_SYS_MEM_BASE (KSEG1ADDR(0x01000000)) /* AVALANCHE ADSL Mem Base */ ++#define AVALANCHE_BROADBAND_INTERFACE__BASE (KSEG1ADDR(0x02000000)) /* AVALANCHE BBIF */ ++#define AVALANCHE_ATM_SAR_BASE (KSEG1ADDR(0x03000000)) /* AVALANCHE ATM SAR */ ++#define AVALANCHE_USB_SLAVE_BASE (KSEG1ADDR(0x03400000)) /* AVALANCHE USB SLAVE */ ++#define AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x04000000)) /* AVALANCHE VLYNQ 0 Mem map */ ++#define AVALANCHE_LOW_CPMAC_BASE (KSEG1ADDR(0x08610000)) /* AVALANCHE CPMAC 0 */ ++#define AVALANCHE_EMIF_CONTROL_BASE (KSEG1ADDR(0x08610800)) /* AVALANCHE EMIF */ ++#define AVALANCHE_GPIO_BASE (KSEG1ADDR(0x08610900)) /* AVALANCHE GPIO */ ++#define AVALANCHE_CLOCK_CONTROL_BASE (KSEG1ADDR(0x08610A00)) /* AVALANCHE Clock Control */ ++#define AVALANCHE_WATCHDOG_TIMER_BASE (KSEG1ADDR(0x08610B00)) /* AVALANCHE Watch Dog Timer */ ++#define AVALANCHE_TIMER0_BASE (KSEG1ADDR(0x08610C00)) /* AVALANCHE Timer 1 */ ++#define AVALANCHE_TIMER1_BASE (KSEG1ADDR(0x08610D00)) /* AVALANCHE Timer 2 */ ++#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */ ++#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 0 */ ++#define AVALANCHE_I2C_BASE (KSEG1ADDR(0x08611000)) /* AVALANCHE I2C */ ++#define AVALANCHE_USB_SLAVE_CONTROL_BASE (KSEG1ADDR(0x08611200)) /* AVALANCHE USB DMA */ ++#define AVALANCHE_MCDMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* AVALANCHE MC DMA 0 (channels 0-3) */ ++#define AVALANCHE_RESET_CONTROL_BASE (KSEG1ADDR(0x08611600)) /* AVALANCHE Reset Control */ ++#define AVALANCHE_BIST_CONTROL_BASE (KSEG1ADDR(0x08611700)) /* AVALANCHE BIST Control */ ++#define AVALANCHE_LOW_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611800)) /* AVALANCHE VLYNQ0 Control */ ++#define AVALANCHE_DEVICE_CONFIG_LATCH_BASE (KSEG1ADDR(0x08611A00)) /* AVALANCHE Device Config Latch */ ++#define AVALANCHE_HIGH_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611C00)) /* AVALANCHE VLYNQ1 Control */ ++#define AVALANCHE_MDIO_BASE (KSEG1ADDR(0x08611E00)) /* AVALANCHE MDIO */ ++#define AVALANCHE_FSER_BASE (KSEG1ADDR(0x08612000)) /* AVALANCHE FSER base */ ++#define AVALANCHE_INTC_BASE (KSEG1ADDR(0x08612400)) /* AVALANCHE INTC */ ++#define AVALANCHE_HIGH_CPMAC_BASE (KSEG1ADDR(0x08612800)) /* AVALANCHE CPMAC 1 */ ++#define AVALANCHE_HIGH_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x0C000000)) /* AVALANCHE VLYNQ 1 Mem map */ ++ ++#define AVALANCHE_SDRAM_BASE 0x14000000UL ++ ++ ++/*---------------------------------------------------- ++ * Sangam Interrupt Map (Primary Interrupts) ++ *--------------------------------------------------*/ ++ ++#define AVALANCHE_UNIFIED_SECONDARY_INT 0 ++#define AVALANCHE_EXT_INT_0 1 ++#define AVALANCHE_EXT_INT_1 2 ++/* Line# 3 to 4 are reserved */ ++#define AVALANCHE_TIMER_0_INT 5 ++#define AVALANCHE_TIMER_1_INT 6 ++#define AVALANCHE_UART0_INT 7 ++#define AVALANCHE_UART1_INT 8 ++#define AVALANCHE_DMA_INT0 9 ++#define AVALANCHE_DMA_INT1 10 ++/* Line# 11 to 14 are reserved */ ++#define AVALANCHE_ATM_SAR_INT 15 ++/* Line# 16 to 18 are reserved */ ++#define AVALANCHE_LOW_CPMAC_INT 19 ++/* Line# 20 is reserved */ ++#define AVALANCHE_LOW_VLYNQ_INT 21 ++#define AVALANCHE_CODEC_WAKEUP_INT 22 ++/* Line# 23 is reserved */ ++#define AVALANCHE_USB_SLAVE_INT 24 ++#define AVALANCHE_HIGH_VLYNQ_INT 25 ++/* Line# 26 to 27 are reserved */ ++#define AVALANCHE_UNIFIED_PHY_INT 28 ++#define AVALANCHE_I2C_INT 29 ++#define AVALANCHE_DMA_INT2 30 ++#define AVALANCHE_DMA_INT3 31 ++/* Line# 32 is reserved */ ++#define AVALANCHE_HIGH_CPMAC_INT 33 ++/* Line# 34 to 36 is reserved */ ++#define AVALANCHE_VDMA_VT_RX_INT 37 ++#define AVALANCHE_VDMA_VT_TX_INT 38 ++#define AVALANCHE_ADSL_SUB_SYSTEM_INT 39 ++ ++ ++#define AVALANCHE_EMIF_INT 47 ++ ++ ++ ++/*----------------------------------------------------------- ++ * Sangam's Reset Bits ++ *---------------------------------------------------------*/ ++ ++#define AVALANCHE_UART0_RESET_BIT 0 ++#define AVALANCHE_UART1_RESET_BIT 1 ++#define AVALANCHE_I2C_RESET_BIT 2 ++#define AVALANCHE_TIMER0_RESET_BIT 3 ++#define AVALANCHE_TIMER1_RESET_BIT 4 ++/* Reset bit 5 is reserved. */ ++#define AVALANCHE_GPIO_RESET_BIT 6 ++#define AVALANCHE_ADSL_SUB_SYS_RESET_BIT 7 ++#define AVALANCHE_USB_SLAVE_RESET_BIT 8 ++#define AVALANCHE_ATM_SAR_RESET_BIT 9 ++/* Reset bit 10 is reserved. */ ++#define AVALANCHE_VDMA_VT_RESET_BIT 11 ++#define AVALANCHE_FSER_RESET_BIT 12 ++/* Reset bit 13 to 15 are reserved */ ++#define AVALANCHE_HIGH_VLYNQ_RESET_BIT 16 ++#define AVALANCHE_LOW_CPMAC_RESET_BIT 17 ++#define AVALANCHE_MCDMA_RESET_BIT 18 ++#define AVALANCHE_BIST_RESET_BIT 19 ++#define AVALANCHE_LOW_VLYNQ_RESET_BIT 20 ++#define AVALANCHE_HIGH_CPMAC_RESET_BIT 21 ++#define AVALANCHE_MDIO_RESET_BIT 22 ++#define AVALANCHE_ADSL_SUB_SYS_DSP_RESET_BIT 23 ++/* Reset bit 24 to 25 are reserved */ ++#define AVALANCHE_LOW_EPHY_RESET_BIT 26 ++/* Reset bit 27 to 31 are reserved */ ++ ++ ++#define AVALANCHE_POWER_MODULE_USBSP 0 ++#define AVALANCHE_POWER_MODULE_WDTP 1 ++#define AVALANCHE_POWER_MODULE_UT0P 2 ++#define AVALANCHE_POWER_MODULE_UT1P 3 ++#define AVALANCHE_POWER_MODULE_IICP 4 ++#define AVALANCHE_POWER_MODULE_VDMAP 5 ++#define AVALANCHE_POWER_MODULE_GPIOP 6 ++#define AVALANCHE_POWER_MODULE_VLYNQ1P 7 ++#define AVALANCHE_POWER_MODULE_SARP 8 ++#define AVALANCHE_POWER_MODULE_ADSLP 9 ++#define AVALANCHE_POWER_MODULE_EMIFP 10 ++#define AVALANCHE_POWER_MODULE_ADSPP 12 ++#define AVALANCHE_POWER_MODULE_RAMP 13 ++#define AVALANCHE_POWER_MODULE_ROMP 14 ++#define AVALANCHE_POWER_MODULE_DMAP 15 ++#define AVALANCHE_POWER_MODULE_BISTP 16 ++#define AVALANCHE_POWER_MODULE_TIMER0P 18 ++#define AVALANCHE_POWER_MODULE_TIMER1P 19 ++#define AVALANCHE_POWER_MODULE_EMAC0P 20 ++#define AVALANCHE_POWER_MODULE_EMAC1P 22 ++#define AVALANCHE_POWER_MODULE_EPHYP 24 ++#define AVALANCHE_POWER_MODULE_VLYNQ0P 27 + -+typedef enum TNETD73XX_WAKEUP_CTRL_tag -+{ -+ WAKEUP_DISABLED = 0, -+ WAKEUP_ENABLED -+} TNETD73XX_WAKEUP_CTRL_T; + -+typedef enum TNETD73XX_WAKEUP_POLARITY_tag -+{ -+ WAKEUP_ACTIVE_HIGH = 0, -+ WAKEUP_ACTIVE_LOW -+} TNETD73XX_WAKEUP_POLARITY_T; + -+void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int, -+ TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl, -+ TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity); + -+/***************************************************************************** -+ * FSER Control -+ *****************************************************************************/ -+ -+typedef enum TNETD73XX_FSER_MODE_tag -+{ -+ FSER_I2C = 0, -+ FSER_UART = 1 -+} TNETD73XX_FSER_MODE_T; + -+void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode); ++/* ++ * Sangam board vectors ++ */ + -+/***************************************************************************** -+ * Clock Control -+ *****************************************************************************/ ++#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE)) ++#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE)) + -+#define CLK_MHZ(x) ( (x) * 1000000 ) ++/*----------------------------------------------------------------------------- ++ * Sangam's system register. ++ * ++ *---------------------------------------------------------------------------*/ ++#define AVALANCHE_DCL_BOOTCR (KSEG1ADDR(0x08611A00)) ++#define AVALANCHE_EMIF_SDRAM_CFG (AVALANCHE_EMIF_CONTROL_BASE + 0x8) ++#define AVALANCHE_RST_CTRL_PRCR (KSEG1ADDR(0x08611600)) ++#define AVALANCHE_RST_CTRL_SWRCR (KSEG1ADDR(0x08611604)) ++#define AVALANCHE_RST_CTRL_RSR (KSEG1ADDR(0x08611600)) ++ ++#define AVALANCHE_POWER_CTRL_PDCR (KSEG1ADDR(0x08610A00)) ++#define AVALANCHE_WAKEUP_CTRL_WKCR (KSEG1ADDR(0x08610A0C)) ++ ++#define AVALANCHE_GPIO_DATA_IN (AVALANCHE_GPIO_BASE + 0x0) ++#define AVALANCHE_GPIO_DATA_OUT (AVALANCHE_GPIO_BASE + 0x4) ++#define AVALANCHE_GPIO_DIR (AVALANCHE_GPIO_BASE + 0x8) ++#define AVALANCHE_GPIO_ENBL (AVALANCHE_GPIO_BASE + 0xC) ++#define AVALANCHE_CVR (AVALANCHE_GPIO_BASE + 0x14) + -+typedef enum TNETD73XX_CLKC_ID_tag -+{ -+ CLKC_SYS = 0, -+ CLKC_MIPS, -+ CLKC_USB, -+ CLKC_ADSLSS -+} TNETD73XX_CLKC_ID_T; ++/* ++ * Yamon Prom print address. ++ */ ++#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500)) ++#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */ ++#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34) + -+void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in); -+TNETD73XX_ERR tnetd73xx_clkc_set_freq(TNETD73XX_CLKC_ID_T clk_id, u32 output_freq); -+u32 tnetd73xx_clkc_get_freq(TNETD73XX_CLKC_ID_T clk_id); ++#define AVALANCHE_BASE_BAUD ( 3686400 / 16 ) + -+/***************************************************************************** -+ * GPIO Control -+ *****************************************************************************/ ++#define AVALANCHE_GPIO_PIN_COUNT 32 ++#define AVALANCHE_GPIO_OFF_MAP {0xF34FFFC0} + -+typedef enum TNETD73XX_GPIO_PIN_tag -+{ -+ GPIO_UART0_RD = 0, -+ GPIO_UART0_TD = 1, -+ GPIO_UART0_RTS = 2, -+ GPIO_UART0_CTS = 3, -+ GPIO_FSER_CLK = 4, -+ GPIO_FSER_D = 5, -+ GPIO_EXT_AFE_SCLK = 6, -+ GPIO_EXT_AFE_TX_FS = 7, -+ GPIO_EXT_AFE_TXD = 8, -+ GPIO_EXT_AFE_RS_FS = 9, -+ GPIO_EXT_AFE_RXD1 = 10, -+ GPIO_EXT_AFE_RXD0 = 11, -+ GPIO_EXT_AFE_CDIN = 12, -+ GPIO_EXT_AFE_CDOUT = 13, -+ GPIO_EPHY_SPEED100 = 14, -+ GPIO_EPHY_LINKON = 15, -+ GPIO_EPHY_ACTIVITY = 16, -+ GPIO_EPHY_FDUPLEX = 17, -+ GPIO_EINT0 = 18, -+ GPIO_EINT1 = 19, -+ GPIO_MBSP0_TCLK = 20, -+ GPIO_MBSP0_RCLK = 21, -+ GPIO_MBSP0_RD = 22, -+ GPIO_MBSP0_TD = 23, -+ GPIO_MBSP0_RFS = 24, -+ GPIO_MBSP0_TFS = 25, -+ GPIO_MII_DIO = 26, -+ GPIO_MII_DCLK = 27, -+} TNETD73XX_GPIO_PIN_T; -+ -+typedef enum TNETD73XX_GPIO_PIN_MODE_tag -+{ -+ FUNCTIONAL_PIN = 0, -+ GPIO_PIN = 1 -+} TNETD73XX_GPIO_PIN_MODE_T; ++#include "sangam_boards.h" + -+typedef enum TNETD73XX_GPIO_PIN_DIRECTION_tag -+{ -+ GPIO_OUTPUT_PIN = 0, -+ GPIO_INPUT_PIN = 1 -+} TNETD73XX_GPIO_PIN_DIRECTION_T; -+ -+void tnetd73xx_gpio_init(void); -+void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin, -+ TNETD73XX_GPIO_PIN_MODE_T pin_mode, -+ TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction); -+void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value); -+int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin); -+ -+/* TNETD73XX Revision */ -+u32 tnetd73xx_get_revision(void); -+ -+#endif /* __TNETD73XX_MISC_H__ */ -diff -urN linux.old/include/asm-mips/io.h linux.dev/include/asm-mips/io.h ---- linux.old/include/asm-mips/io.h 2005-07-07 05:38:31.416480768 +0200 -+++ linux.dev/include/asm-mips/io.h 2005-07-07 04:39:14.434224000 +0200 ++#endif /*_SANGAM_H_ */ +diff -urN kernel-base/include/asm-mips/io.h kernel-current/include/asm-mips/io.h +--- kernel-base/include/asm-mips/io.h 2005-07-10 03:00:44.797179400 +0200 ++++ kernel-current/include/asm-mips/io.h 2005-07-10 06:40:39.624260000 +0200 @@ -63,8 +63,12 @@ #ifdef CONFIG_64BIT_PHYS_ADDR #define page_to_phys(page) ((u64)(page - mem_map) << PAGE_SHIFT) @@ -5595,9 +4254,9 @@ diff -urN linux.old/include/asm-mips/io.h linux.dev/include/asm-mips/io.h #define IO_SPACE_LIMIT 0xffff -diff -urN linux.old/include/asm-mips/irq.h linux.dev/include/asm-mips/irq.h ---- linux.old/include/asm-mips/irq.h 2005-07-07 05:38:31.424479552 +0200 -+++ linux.dev/include/asm-mips/irq.h 2005-07-07 04:39:14.435224000 +0200 +diff -urN kernel-base/include/asm-mips/irq.h kernel-current/include/asm-mips/irq.h +--- kernel-base/include/asm-mips/irq.h 2005-07-10 03:00:44.798179248 +0200 ++++ kernel-current/include/asm-mips/irq.h 2005-07-10 06:40:39.624260000 +0200 @@ -14,7 +14,12 @@ #include #include @@ -5611,9 +4270,9 @@ diff -urN linux.old/include/asm-mips/irq.h linux.dev/include/asm-mips/irq.h #ifdef CONFIG_I8259 static inline int irq_cannonicalize(int irq) -diff -urN linux.old/include/asm-mips/page.h linux.dev/include/asm-mips/page.h ---- linux.old/include/asm-mips/page.h 2005-07-07 05:38:31.426479248 +0200 -+++ linux.dev/include/asm-mips/page.h 2005-07-07 04:39:14.435224000 +0200 +diff -urN kernel-base/include/asm-mips/page.h kernel-current/include/asm-mips/page.h +--- kernel-base/include/asm-mips/page.h 2005-07-10 03:00:44.798179248 +0200 ++++ kernel-current/include/asm-mips/page.h 2005-07-10 06:40:39.625260000 +0200 @@ -129,7 +129,11 @@ #define __pa(x) ((unsigned long) (x) - PAGE_OFFSET) @@ -5626,9 +4285,9 @@ diff -urN linux.old/include/asm-mips/page.h linux.dev/include/asm-mips/page.h #define VALID_PAGE(page) ((page - mem_map) < max_mapnr) #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ -diff -urN linux.old/include/asm-mips/pgtable-32.h linux.dev/include/asm-mips/pgtable-32.h ---- linux.old/include/asm-mips/pgtable-32.h 2005-07-07 05:38:31.434478032 +0200 -+++ linux.dev/include/asm-mips/pgtable-32.h 2005-07-07 04:39:14.435224000 +0200 +diff -urN kernel-base/include/asm-mips/pgtable-32.h kernel-current/include/asm-mips/pgtable-32.h +--- kernel-base/include/asm-mips/pgtable-32.h 2005-07-10 03:00:44.798179248 +0200 ++++ kernel-current/include/asm-mips/pgtable-32.h 2005-07-10 06:40:39.625260000 +0200 @@ -108,7 +108,18 @@ * and a page entry and page directory to the page they refer to. */ @@ -5669,9 +4328,9 @@ diff -urN linux.old/include/asm-mips/pgtable-32.h linux.dev/include/asm-mips/pgt #define pte_page(x) (mem_map+((unsigned long)(((x).pte_low >> (PAGE_SHIFT+2))))) #define __mk_pte(page_nr,pgprot) __pte(((page_nr) << (PAGE_SHIFT+2)) | pgprot_val(pgprot)) #else -diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h ---- linux.old/include/asm-mips/serial.h 2005-07-07 05:38:31.470472560 +0200 -+++ linux.dev/include/asm-mips/serial.h 2005-07-07 04:39:14.436223000 +0200 +diff -urN kernel-base/include/asm-mips/serial.h kernel-current/include/asm-mips/serial.h +--- kernel-base/include/asm-mips/serial.h 2005-07-10 03:00:44.799179096 +0200 ++++ kernel-current/include/asm-mips/serial.h 2005-07-10 06:40:39.625260000 +0200 @@ -65,6 +65,15 @@ #define C_P(card,port) (((card)<<6|(port)<<3) + 1) @@ -5679,8 +4338,8 @@ diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial. +#ifdef CONFIG_AR7 +#include +#define AR7_SERIAL_PORT_DEFNS \ -+ { 0, AVALANCHE_BASE_BAUD, AVALANCHE_UART0_REGS_BASE, LNXINTNUM(AVALANCHE_UART0_INT), STD_COM_FLAGS }, \ -+ { 0, AVALANCHE_BASE_BAUD, AVALANCHE_UART1_REGS_BASE, LNXINTNUM(AVALANCHE_UART1_INT), STD_COM_FLAGS }, ++ { 0, AR7_BASE_BAUD, AR7_UART0_REGS_BASE, LNXINTNUM(AVALANCHE_UART0_INT), STD_COM_FLAGS }, \ ++ { 0, AR7_BASE_BAUD, AR7_UART1_REGS_BASE, LNXINTNUM(AVALANCHE_UART1_INT), STD_COM_FLAGS }, +#else +#define AR7_SERIAL_PORT_DEFNS +#endif @@ -5696,9 +4355,9 @@ diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial. ATLAS_SERIAL_PORT_DEFNS \ AU1000_SERIAL_PORT_DEFNS \ COBALT_SERIAL_PORT_DEFNS \ -diff -urN linux.old/Makefile linux.dev/Makefile ---- linux.old/Makefile 2005-07-07 05:38:31.320495360 +0200 -+++ linux.dev/Makefile 2005-07-07 04:39:14.501214000 +0200 +diff -urN kernel-base/Makefile kernel-current/Makefile +--- kernel-base/Makefile 2005-07-10 03:00:44.799179096 +0200 ++++ kernel-current/Makefile 2005-07-10 06:40:39.626260000 +0200 @@ -91,7 +91,7 @@ CPPFLAGS := -D__KERNEL__ -I$(HPATH)