X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/a5bba4d8fbc31bd5d21bfb44400cbc2025d51e35..9d012c4aae5fbbbb0a87700d18f2a7f7374e7ddf:/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h

diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
index 0a3167862..47ad8a4ba 100644
--- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
@@ -70,15 +70,21 @@
 #define AR91XX_WMAC_BASE	(AR71XX_APB_BASE + 0x000C0000)
 #define AR91XX_WMAC_SIZE	0x30000
 
+#define AR933X_UART_BASE	(AR71XX_APB_BASE + 0x00020000)
+#define AR933X_UART_SIZE	0x14
+
+#define AR934X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+#define AR934X_WMAC_SIZE	0x20000
+
 #define AR71XX_MEM_SIZE_MIN	0x0200000
 #define AR71XX_MEM_SIZE_MAX	0x10000000
 
 #define AR71XX_CPU_IRQ_BASE	0
 #define AR71XX_MISC_IRQ_BASE	8
-#define AR71XX_MISC_IRQ_COUNT	8
-#define AR71XX_GPIO_IRQ_BASE	16
+#define AR71XX_MISC_IRQ_COUNT	32
+#define AR71XX_GPIO_IRQ_BASE	40
 #define AR71XX_GPIO_IRQ_COUNT	32
-#define AR71XX_PCI_IRQ_BASE     48
+#define AR71XX_PCI_IRQ_BASE	72
 #define AR71XX_PCI_IRQ_COUNT	8
 
 #define AR71XX_CPU_IRQ_IP2	(AR71XX_CPU_IRQ_BASE + 2)
@@ -96,6 +102,11 @@
 #define AR71XX_MISC_IRQ_PERFC	(AR71XX_MISC_IRQ_BASE + 5)
 #define AR71XX_MISC_IRQ_OHCI	(AR71XX_MISC_IRQ_BASE + 6)
 #define AR71XX_MISC_IRQ_DMA	(AR71XX_MISC_IRQ_BASE + 7)
+#define AR71XX_MISC_IRQ_TIMER2	(AR71XX_MISC_IRQ_BASE + 8)
+#define AR71XX_MISC_IRQ_TIMER3	(AR71XX_MISC_IRQ_BASE + 9)
+#define AR71XX_MISC_IRQ_TIMER4	(AR71XX_MISC_IRQ_BASE + 10)
+#define AR71XX_MISC_IRQ_DDR_PERF	(AR71XX_MISC_IRQ_BASE + 11)
+#define AR71XX_MISC_IRQ_ENET_LINK	(AR71XX_MISC_IRQ_BASE + 12)
 
 #define AR71XX_GPIO_IRQ(_x)	(AR71XX_GPIO_IRQ_BASE + (_x))
 
@@ -107,7 +118,7 @@
 extern u32 ar71xx_ahb_freq;
 extern u32 ar71xx_cpu_freq;
 extern u32 ar71xx_ddr_freq;
-extern u32 ar934x_ref_freq;
+extern u32 ar71xx_ref_freq;
 
 enum ar71xx_soc_type {
 	AR71XX_SOC_UNKNOWN,
@@ -119,6 +130,8 @@ enum ar71xx_soc_type {
 	AR71XX_SOC_AR7242,
 	AR71XX_SOC_AR9130,
 	AR71XX_SOC_AR9132,
+	AR71XX_SOC_AR9330,
+	AR71XX_SOC_AR9331,
 	AR71XX_SOC_AR9341,
 	AR71XX_SOC_AR9342,
 	AR71XX_SOC_AR9344,
@@ -158,6 +171,8 @@ extern enum ar71xx_soc_type ar71xx_soc;
 #define AR724X_DDR_DIV_SHIFT		22
 #define AR724X_DDR_DIV_MASK		0x3
 
+#define AR7242_PLL_REG_ETH0_INT_CLOCK	0x2c
+
 #define AR91XX_PLL_REG_CPU_CONFIG	0x00
 #define AR91XX_PLL_REG_ETH_CONFIG	0x04
 #define AR91XX_PLL_REG_ETH0_INT_CLOCK	0x14
@@ -422,6 +437,12 @@ static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
 
 #define AR91XX_GPIO_COUNT	22
 
+#define AR934X_GPIO_FUNC_SPI_CS_1_EN	BIT(14)
+#define AR934X_GPIO_FUNC_SPI_CS_0_EN	BIT(13)
+
+#define AR934X_GPIO_COUNT		32
+#define AR934X_GPIO_FUNC_DDR_DQOE_EN	BIT(17)
+
 extern void __iomem *ar71xx_gpio_base;
 
 static inline void ar71xx_gpio_wr(unsigned reg, u32 value)
@@ -465,6 +486,12 @@ void ar71xx_gpio_function_setup(u32 set, u32 clear);
 #define AR91XX_DDR_REG_FLUSH_USB	0x84
 #define AR91XX_DDR_REG_FLUSH_WMAC	0x88
 
+#define AR934X_DDR_REG_FLUSH_GE0	0x9c
+#define AR934X_DDR_REG_FLUSH_GE1	0xa0
+#define AR934X_DDR_REG_FLUSH_USB	0xa4
+#define AR934X_DDR_REG_FLUSH_PCIE	0xa8
+
+
 #define PCI_WIN0_OFFS	0x10000000
 #define PCI_WIN1_OFFS	0x11000000
 #define PCI_WIN2_OFFS	0x12000000
@@ -564,6 +591,11 @@ void ar71xx_ddr_flush(u32 reg);
 #define WDOG_CTRL_ACTION_NMI		2	/* NMI */
 #define WDOG_CTRL_ACTION_FCR		3	/* full chip reset */
 
+#define MISC_INT_ENET_LINK		BIT(12)
+#define MISC_INT_DDR_PERF		BIT(11)
+#define MISC_INT_TIMER4		BIT(10)
+#define MISC_INT_TIMER3		BIT(9)
+#define MISC_INT_TIMER2		BIT(8)
 #define MISC_INT_DMA			BIT(7)
 #define MISC_INT_OHCI			BIT(6)
 #define MISC_INT_PERFC			BIT(5)
@@ -614,6 +646,8 @@ void ar71xx_ddr_flush(u32 reg);
 #define REV_ID_MAJOR_AR7240	0x00c0
 #define REV_ID_MAJOR_AR7241	0x0100
 #define REV_ID_MAJOR_AR7242	0x1100
+#define REV_ID_MAJOR_AR9330	0x0110
+#define REV_ID_MAJOR_AR9331	0x1110
 #define REV_ID_MAJOR_AR9341	0x0120
 #define REV_ID_MAJOR_AR9342	0x1120
 #define REV_ID_MAJOR_AR9344	0x2120
@@ -633,6 +667,8 @@ void ar71xx_ddr_flush(u32 reg);
 
 #define AR724X_REV_ID_REVISION_MASK	0x3
 
+#define AR933X_REV_ID_REVISION_MASK	0xf
+
 #define AR934X_REV_ID_REVISION_MASK	0xf
 
 extern void __iomem *ar71xx_reset_base;