X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/ab0a79714f445ae17d1ad601ff0628e75f31a430..2122c93af5a8b5b8d2c4c2bdb6274fc1eaf42a62:/target/linux/ramips/files/arch/mips/ralink/common/setup.c diff --git a/target/linux/ramips/files/arch/mips/ralink/common/setup.c b/target/linux/ramips/files/arch/mips/ralink/common/setup.c index 6440ccb01..877d0b7de 100644 --- a/target/linux/ramips/files/arch/mips/ralink/common/setup.c +++ b/target/linux/ramips/files/arch/mips/ralink/common/setup.c @@ -12,13 +12,81 @@ #include #include #include +#include +#include #include + #include +#include +#include + +unsigned char ramips_sys_type[RAMIPS_SYS_TYPE_LEN]; + +const char *get_system_type(void) +{ + return ramips_sys_type; +} + +static void __init detect_mem_size(void) +{ + unsigned long size; + + for (size = RALINK_SOC_MEM_SIZE_MIN; size < RALINK_SOC_MEM_SIZE_MAX; + size <<= 1 ) { + if (!memcmp(detect_mem_size, + detect_mem_size + size, 1024)) + break; + } + + add_memory_region(RALINK_SOC_SDRAM_BASE, size, BOOT_MEM_RAM); +} + +void __init ramips_early_serial_setup(int line, unsigned base, unsigned freq, + unsigned irq) +{ + struct uart_port p; + int err; + + memset(&p, 0, sizeof(p)); + p.flags = UPF_SKIP_TEST; + p.iotype = UPIO_AU; + p.uartclk = freq; + p.regshift = 2; + p.type = PORT_16550A; + + p.mapbase = base; + p.membase = ioremap_nocache(p.mapbase, PAGE_SIZE); + p.line = line; + p.irq = irq; + + err = early_serial_setup(&p); + if (err) + printk(KERN_ERR "early serial%d registration failed %d\n", + line, err); +} void __init plat_mem_setup(void) { set_io_port_base(KSEG1); + detect_mem_size(); ramips_soc_setup(); } + +__setup("board=", mips_machtype_setup); + +static int __init ramips_machine_setup(void) +{ + mips_machine_setup(); + return 0; +} + +arch_initcall(ramips_machine_setup); + +static void __init ramips_generic_init(void) +{ +} + +MIPS_MACHINE(RAMIPS_MACH_GENERIC, "Generic", "Generic Ralink board", + ramips_generic_init);