X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/b1704a799d743388d45be6aef04ec57909aa73c4..62be67eb01c9ee1941f8a6074fee4b297f92b6d5:/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c?ds=sidebyside

diff --git a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
index 7d0eee9db..1014acc8c 100644
--- a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
+++ b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
@@ -107,7 +107,7 @@ int ar71xx_pci_be_handler(int is_fixup)
 		__raw_writel(ahb_err, base + PCI_REG_AHB_ERR);
 	}
 
-	return ((ahb_err | pci_err) ? 1 : 0);
+	return (ahb_err | pci_err) ? 1 : 0;
 }
 
 static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
@@ -136,6 +136,7 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 	static u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0};
 	unsigned long flags;
 	u32 data;
+	int retry = 0;
 	int ret;
 
 	ret = PCIBIOS_SUCCESSFUL;
@@ -143,6 +144,7 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 	DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d\n", bus->number,
 			PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
 
+retry:
 	spin_lock_irqsave(&ar71xx_pci_lock, flags);
 
 	if (bus->number == 0 && devfn == 0) {
@@ -176,6 +178,14 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 
 	*value = (data >> (8 * (where & 3))) & mask[size & 7];
 
+	/*
+	 * PCI controller bug: sometimes reads to the PCI_COMMAND register
+	 * return 0xffff, even though the PCI trace shows the correct value.
+	 * Work around this by retrying reads to this register
+	 */
+	if (where == PCI_COMMAND && (*value & 0xffff) == 0xffff && retry++ < 2)
+		goto retry;
+
 	return ret;
 }
 
@@ -363,11 +373,9 @@ static void __init ar71xx_pci_irq_init(void)
 	__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
 
 	for (i = AR71XX_PCI_IRQ_BASE;
-	     i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
-		irq_desc[i].status = IRQ_DISABLED;
+	     i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++)
 		set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip,
 					 handle_level_irq);
-	}
 
 	set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar71xx_pci_irq_handler);
 }