X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/c363de958e3fd2e75e3743d484de8fdaec815294..097b43c34c6d4d5c07e382cf095d2f3ca1542d0c:/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h

diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
index d21df49d6..ce9523d3f 100644
--- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
@@ -112,6 +112,8 @@ enum ar71xx_soc_type {
 	AR71XX_SOC_AR7141,
 	AR71XX_SOC_AR7161,
 	AR71XX_SOC_AR7240,
+	AR71XX_SOC_AR7241,
+	AR71XX_SOC_AR7242,
 	AR71XX_SOC_AR9130,
 	AR71XX_SOC_AR9132
 };
@@ -425,14 +427,21 @@ void ar71xx_ddr_flush(u32 reg);
 #define RESET_MODULE_PCI_BUS		BIT(1)
 #define RESET_MODULE_PCI_CORE		BIT(0)
 
+#define AR724X_RESET_GE1_MDIO		BIT(23)
+#define AR724X_RESET_GE0_MDIO		BIT(22)
 #define AR724X_RESET_PCIE_PHY_SERIAL	BIT(10)
 #define AR724X_RESET_PCIE_PHY		BIT(7)
 #define AR724X_RESET_PCIE		BIT(6)
-
-#define REV_ID_MAJOR_MASK	0xf0
-#define REV_ID_MAJOR_AR71XX	0xa0
-#define REV_ID_MAJOR_AR913X	0xb0
-#define REV_ID_MAJOR_AR724X	0xc0
+#define AR724X_RESET_USB_HOST		BIT(5)
+#define AR724X_RESET_USB_PHY		BIT(4)
+#define AR724X_RESET_USBSUS_OVERRIDE	BIT(3)
+
+#define REV_ID_MAJOR_MASK	0xfff0
+#define REV_ID_MAJOR_AR71XX	0x00a0
+#define REV_ID_MAJOR_AR913X	0x00b0
+#define REV_ID_MAJOR_AR7240	0x00c0
+#define REV_ID_MAJOR_AR7241	0x0100
+#define REV_ID_MAJOR_AR7242	0x1100
 
 #define AR71XX_REV_ID_MINOR_MASK	0x3
 #define AR71XX_REV_ID_MINOR_AR7130	0x0