X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/c5000fc993567f7898b25d22c2944c6152b7d152..7c4adb453ca50171911eca8ef59a21b08c78e687:/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h

diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
index ab00d19e1..7c99dba66 100644
--- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
@@ -70,6 +70,14 @@
 #define AR91XX_WMAC_BASE	(AR71XX_APB_BASE + 0x000C0000)
 #define AR91XX_WMAC_SIZE	0x30000
 
+#define AR933X_UART_BASE	(AR71XX_APB_BASE + 0x00020000)
+#define AR933X_UART_SIZE	0x14
+#define AR933X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+#define AR933X_WMAC_SIZE	0x20000
+
+#define AR934X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
+#define AR934X_WMAC_SIZE	0x20000
+
 #define AR71XX_MEM_SIZE_MIN	0x0200000
 #define AR71XX_MEM_SIZE_MAX	0x10000000
 
@@ -112,7 +120,7 @@
 extern u32 ar71xx_ahb_freq;
 extern u32 ar71xx_cpu_freq;
 extern u32 ar71xx_ddr_freq;
-extern u32 ar934x_ref_freq;
+extern u32 ar71xx_ref_freq;
 
 enum ar71xx_soc_type {
 	AR71XX_SOC_UNKNOWN,
@@ -124,6 +132,8 @@ enum ar71xx_soc_type {
 	AR71XX_SOC_AR7242,
 	AR71XX_SOC_AR9130,
 	AR71XX_SOC_AR9132,
+	AR71XX_SOC_AR9330,
+	AR71XX_SOC_AR9331,
 	AR71XX_SOC_AR9341,
 	AR71XX_SOC_AR9342,
 	AR71XX_SOC_AR9344,
@@ -163,6 +173,8 @@ extern enum ar71xx_soc_type ar71xx_soc;
 #define AR724X_DDR_DIV_SHIFT		22
 #define AR724X_DDR_DIV_MASK		0x3
 
+#define AR7242_PLL_REG_ETH0_INT_CLOCK	0x2c
+
 #define AR91XX_PLL_REG_CPU_CONFIG	0x00
 #define AR91XX_PLL_REG_ETH_CONFIG	0x04
 #define AR91XX_PLL_REG_ETH0_INT_CLOCK	0x14
@@ -178,6 +190,24 @@ extern enum ar71xx_soc_type ar71xx_soc;
 #define AR91XX_ETH0_PLL_SHIFT		20
 #define AR91XX_ETH1_PLL_SHIFT		22
 
+#define AR933X_PLL_CPU_CONFIG_REG	0x00
+#define AR933X_PLL_CLOCK_CTRL_REG	0x08
+
+#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT	10
+#define AR933X_PLL_CPU_CONFIG_NINT_MASK		0x3f
+#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT	16
+#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT	23
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK	0x7
+
+#define AR933X_PLL_CLOCK_CTRL_BYPASS		BIT(2)
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT	5
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK	0x3
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT	10
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK	0x3
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT	15
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK	0x7
+
 #define AR934X_PLL_REG_CPU_CONFIG	0x00
 #define AR934X_PLL_REG_DDR_CTRL_CLOCK	0x8
 
@@ -427,6 +457,14 @@ static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
 
 #define AR91XX_GPIO_COUNT	22
 
+#define AR933X_GPIO_COUNT	30
+
+#define AR934X_GPIO_FUNC_SPI_CS_1_EN	BIT(14)
+#define AR934X_GPIO_FUNC_SPI_CS_0_EN	BIT(13)
+
+#define AR934X_GPIO_COUNT		32
+#define AR934X_GPIO_FUNC_DDR_DQOE_EN	BIT(17)
+
 extern void __iomem *ar71xx_gpio_base;
 
 static inline void ar71xx_gpio_wr(unsigned reg, u32 value)
@@ -470,6 +508,11 @@ void ar71xx_gpio_function_setup(u32 set, u32 clear);
 #define AR91XX_DDR_REG_FLUSH_USB	0x84
 #define AR91XX_DDR_REG_FLUSH_WMAC	0x88
 
+#define AR933X_DDR_REG_FLUSH_GE0	0x7c
+#define AR933X_DDR_REG_FLUSH_GE1	0x80
+#define AR933X_DDR_REG_FLUSH_USB	0x84
+#define AR933X_DDR_REG_FLUSH_WMAC	0x88
+
 #define AR934X_DDR_REG_FLUSH_GE0	0x9c
 #define AR934X_DDR_REG_FLUSH_GE1	0xa0
 #define AR934X_DDR_REG_FLUSH_USB	0xa4
@@ -563,6 +606,10 @@ void ar71xx_ddr_flush(u32 reg);
 
 #define AR724X_RESET_REG_RESET_MODULE		0x1c
 
+#define AR933X_RESET_REG_RESET_MODULE		0x1c
+#define AR933X_RESET_REG_BOOTSTRAP		0xac
+#define AR933X_BOOTSTRAP_REF_CLK_40		BIT(0)
+
 #define AR934X_RESET_REG_RESET_MODULE		0x1c
 #define AR934X_RESET_REG_BOOTSTRAP		0xb0
 /* 0 - 25MHz   1 - 40 MHz */
@@ -624,12 +671,19 @@ void ar71xx_ddr_flush(u32 reg);
 #define AR724X_RESET_USB_PHY		BIT(4)
 #define AR724X_RESET_USBSUS_OVERRIDE	BIT(3)
 
+#define AR933X_RESET_GE1_MDIO		BIT(23)
+#define AR933X_RESET_GE0_MDIO		BIT(22)
+#define AR933X_RESET_GE1_MAC		BIT(13)
+#define AR933X_RESET_GE0_MAC		BIT(9)
+
 #define REV_ID_MAJOR_MASK	0xfff0
 #define REV_ID_MAJOR_AR71XX	0x00a0
 #define REV_ID_MAJOR_AR913X	0x00b0
 #define REV_ID_MAJOR_AR7240	0x00c0
 #define REV_ID_MAJOR_AR7241	0x0100
 #define REV_ID_MAJOR_AR7242	0x1100
+#define REV_ID_MAJOR_AR9330	0x0110
+#define REV_ID_MAJOR_AR9331	0x1110
 #define REV_ID_MAJOR_AR9341	0x0120
 #define REV_ID_MAJOR_AR9342	0x1120
 #define REV_ID_MAJOR_AR9344	0x2120
@@ -649,6 +703,8 @@ void ar71xx_ddr_flush(u32 reg);
 
 #define AR724X_REV_ID_REVISION_MASK	0x3
 
+#define AR933X_REV_ID_REVISION_MASK	0xf
+
 #define AR934X_REV_ID_REVISION_MASK	0xf
 
 extern void __iomem *ar71xx_reset_base;