X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/c680366531724621150ca3d6cbb6d52c0c1b96e2..cf68954004dfda5c4c49dcb79bda1753135b2a6c:/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c

diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c
index 9173b48ad..aa9a74f34 100644
--- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c
@@ -13,46 +13,6 @@
 
 #include "ag71xx.h"
 
-#define PLL_SEC_CONFIG		0x18050004
-#define PLL_ETH0_INT_CLOCK	0x18050010
-#define PLL_ETH1_INT_CLOCK	0x18050014
-#define PLL_ETH_EXT_CLOCK	0x18050018
-
-#define ag71xx_pll_shift(_ag)   (((_ag)->pdev->id) ? 19 : 17)
-#define ag71xx_pll_offset(_ag)	(((_ag)->pdev->id) ? PLL_ETH1_INT_CLOCK \
-						   : PLL_ETH0_INT_CLOCK)
-
-static void ag71xx_set_pll(struct ag71xx *ag, u32 pll_val)
-{
-	void __iomem *pll_reg = ioremap_nocache(ag71xx_pll_offset(ag), 4);
-	void __iomem *pll_cfg = ioremap_nocache(PLL_SEC_CONFIG, 4);
-	u32 s;
-	u32 t;
-
-	s = ag71xx_pll_shift(ag);
-
-	t = __raw_readl(pll_cfg);
-	t &= ~(3 << s);
-	t |=  (2 << s);
-	__raw_writel(t, pll_cfg);
-	udelay(100);
-
-	__raw_writel(pll_val, pll_reg);
-
-	t |= (3 << s);
-	__raw_writel(t, pll_cfg);
-	udelay(100);
-
-	t &= ~(3 << s);
-	__raw_writel(t, pll_cfg);
-	udelay(100);
-	DBG("%s: pll_reg %#x: %#x\n", ag->dev->name,
-			(unsigned int)pll_reg, __raw_readl(pll_reg));
-
-	iounmap(pll_cfg);
-	iounmap(pll_reg);
-}
-
 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
 {
 	switch (ag->speed) {
@@ -67,18 +27,17 @@ static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
 	return "?";
 }
 
-#if 1
-#define PLL_VAL_1000	0x00110000
-#define PLL_VAL_100	0x00001099
-#define PLL_VAL_10	0x00991099
-#else
-#define PLL_VAL_1000	0x01111000
-#define PLL_VAL_100	0x09991000
-#define PLL_VAL_10	0x09991999
-#endif
+#define AR71XX_PLL_VAL_1000	0x00110000
+#define AR71XX_PLL_VAL_100	0x00001099
+#define AR71XX_PLL_VAL_10	0x00991099
+
+#define AR91XX_PLL_VAL_1000	0x1a000000
+#define AR91XX_PLL_VAL_100	0x13000a44
+#define AR91XX_PLL_VAL_10	0x00441099
 
 static void ag71xx_phy_link_update(struct ag71xx *ag)
 {
+	struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 	u32 cfg2;
 	u32 ifctl;
 	u32 pll;
@@ -106,27 +65,31 @@ static void ag71xx_phy_link_update(struct ag71xx *ag)
 	case SPEED_1000:
 		mii_speed =  MII_CTRL_SPEED_1000;
 		cfg2 |= MAC_CFG2_IF_1000;
-		pll = PLL_VAL_1000;
+		pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_1000
+				       : AR71XX_PLL_VAL_1000;
 		fifo5 |= FIFO_CFG5_BM;
 		break;
 	case SPEED_100:
 		mii_speed = MII_CTRL_SPEED_100;
 		cfg2 |= MAC_CFG2_IF_10_100;
 		ifctl |= MAC_IFCTL_SPEED;
-		pll = PLL_VAL_100;
+		pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_100
+				       : AR71XX_PLL_VAL_100;
 		break;
 	case SPEED_10:
 		mii_speed = MII_CTRL_SPEED_10;
 		cfg2 |= MAC_CFG2_IF_10_100;
-		pll = PLL_VAL_10;
+		pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_10
+				       : AR71XX_PLL_VAL_10;
 		break;
 	default:
 		BUG();
 		return;
 	}
 
-	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
-	ag71xx_set_pll(ag, pll);
+	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3,
+			pdata->is_ar91xx ? 0x780fff : 0x008001ff);
+	pdata->set_pll(pll);
 	ag71xx_mii_ctrl_set_speed(ag, mii_speed);
 
 	ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);