X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/d3b0cb38e0ebdf22042b4fb318d0fec22fbd2da2..bf5f735641b53a1e47871f8aa04d2956a427c3bc:/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h

diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h
index 1dd6c2dce..2ae26ef8b 100644
--- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h
@@ -33,9 +33,11 @@
 #define RT2880_SDRAM_BASE	0x08000000
 
 #define RT2880_SYSC_SIZE	0x100
+#define RT2880_TIMER_SIZE	0x100
 #define RT2880_INTC_SIZE	0x100
 #define RT2880_MEMC_SIZE	0x100
 #define RT2880_UART0_SIZE	0x100
+#define RT2880_PIO_SIZE		0x100
 #define RT2880_UART1_SIZE	0x100
 #define RT2880_FLASH1_SIZE	(16 * 1024 * 1024)
 #define RT2880_FLASH0_SIZE	(4 * 1024 * 1024)
@@ -45,6 +47,7 @@
 #define SYSC_REG_CHIP_NAME1	0x004	/* Chip Name 1 */
 #define SYSC_REG_CHIP_ID	0x00c	/* Chip Identification */
 #define SYSC_REG_SYSTEM_CONFIG	0x010	/* System Configuration */
+#define SYSC_REG_CLKCFG		0x030
 #define SYSC_REG_RESET_CTRL	0x034	/* Reset Control*/
 #define SYSC_REG_RESET_STATUS	0x038	/* Reset Status*/
 #define SYSC_REG_GPIO_MODE	0x060	/* GPIO Purpose Select */
@@ -62,6 +65,8 @@
 #define SYSTEM_CONFIG_CPUCLK_280	0x2
 #define SYSTEM_CONFIG_CPUCLK_300	0x3
 
+#define CLKCFG_SRAM_CS_N_WDT	BIT(9)
+
 #define RT2880_RESET_SYSTEM	BIT(0)
 #define RT2880_RESET_TIMER	BIT(1)
 #define RT2880_RESET_INTC	BIT(2)