X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/d5e01e3fd2db04b895d87e4fb83e293b763c0f69..e2bae31171dc8902098c6e79b3f651d2fb4899ef:/package/broadcom-diag/src/gpio.h

diff --git a/package/broadcom-diag/src/gpio.h b/package/broadcom-diag/src/gpio.h
index 16f6ca41c..71917787c 100644
--- a/package/broadcom-diag/src/gpio.h
+++ b/package/broadcom-diag/src/gpio.h
@@ -1,138 +1,153 @@
 #ifndef __DIAG_GPIO_H
 #define __DIAG_GPIO_H
-#include <linux/interrupt.h>
-
-#ifndef BCMDRIVER
-#include <linux/ssb/ssb.h>
-#include <linux/ssb/ssb_driver_chipcommon.h>
-#include <linux/ssb/ssb_driver_extif.h>
-
-extern struct ssb_bus ssb;
 
-#define gpio_op(op, param...) \
-	do { \
-		if (ssb.chipco.dev) \
-			return ssb_chipco_gpio_##op(&ssb.chipco, param); \
-		else if (ssb.extif.dev) \
-			return ssb_extif_gpio_##op(&ssb.extif, param); \
-		else \
-			return 0; \
-	} while (0);
-		
+#include <linux/interrupt.h>
+#include <linux/ssb/ssb_embedded.h>
+#include <linux/gpio.h>
+#include <bcm47xx.h>
 
 static inline u32 gpio_in(void)
 {
-	gpio_op(in, ~0);
+	switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
+	case BCM47XX_BUS_TYPE_SSB:
+		return ssb_gpio_in(&bcm47xx_bus.ssb, ~0);
+#endif
+#ifdef CONFIG_BCM47XX_BCMA
+	case BCM47XX_BUS_TYPE_BCMA:
+		return bcma_chipco_gpio_in(&bcm47xx_bus.bcma.bus.drv_cc, ~0);
+#endif
+	}
+	return -EINVAL;
 }
 
 static inline u32 gpio_out(u32 mask, u32 value)
 {
-	gpio_op(out, mask, value);
+	switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
+	case BCM47XX_BUS_TYPE_SSB:
+		return ssb_gpio_out(&bcm47xx_bus.ssb, mask, value);
+#endif
+#ifdef CONFIG_BCM47XX_BCMA
+	case BCM47XX_BUS_TYPE_BCMA:
+		return bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, mask, value);
+#endif
+	}
+	return -EINVAL;
 }
 
 static inline u32 gpio_outen(u32 mask, u32 value)
 {
-	gpio_op(outen, mask, value);
+	switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
+	case BCM47XX_BUS_TYPE_SSB:
+		ssb_gpio_outen(&bcm47xx_bus.ssb, mask, value);
+		return 0;
+#endif
+#ifdef CONFIG_BCM47XX_BCMA
+	case BCM47XX_BUS_TYPE_BCMA:
+		bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc, mask, value);
+		return 0;
+#endif
+	}
+	return -EINVAL;
 }
 
 static inline u32 gpio_control(u32 mask, u32 value)
 {
-	if (ssb.chipco.dev)
-		return ssb_chipco_gpio_control(&ssb.chipco, mask, value);
-	else
-		return 0;
+	switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
+	case BCM47XX_BUS_TYPE_SSB:
+		return ssb_gpio_control(&bcm47xx_bus.ssb, mask, value);
+#endif
+#ifdef CONFIG_BCM47XX_BCMA
+	case BCM47XX_BUS_TYPE_BCMA:
+		return bcma_chipco_gpio_control(&bcm47xx_bus.bcma.bus.drv_cc, mask, value);
+#endif
+	}
+	return -EINVAL;
 }
 
-static inline u32 gpio_intmask(u32 mask, u32 value)
+static inline u32 gpio_setintmask(u32 mask, u32 value)
 {
-	gpio_op(intmask, mask, value);
+	switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
+	case BCM47XX_BUS_TYPE_SSB:
+		return ssb_gpio_intmask(&bcm47xx_bus.ssb, mask, value);
+#endif
+#ifdef CONFIG_BCM47XX_BCMA
+	case BCM47XX_BUS_TYPE_BCMA:
+		return bcma_chipco_gpio_intmask(&bcm47xx_bus.bcma.bus.drv_cc, mask, value);
+#endif
+	}
+	return -EINVAL;
 }
 
 static inline u32 gpio_intpolarity(u32 mask, u32 value)
 {
-	gpio_op(polarity, mask, value);
+	switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
+	case BCM47XX_BUS_TYPE_SSB:
+		return ssb_gpio_polarity(&bcm47xx_bus.ssb, mask, value);
+#endif
+#ifdef CONFIG_BCM47XX_BCMA
+	case BCM47XX_BUS_TYPE_BCMA:
+		return bcma_chipco_gpio_polarity(&bcm47xx_bus.bcma.bus.drv_cc, mask, value);
+#endif
+	}
+	return -EINVAL;
 }
 
-static void gpio_set_irqenable(int enabled, irqreturn_t (*handler)(int, void *, struct pt_regs *))
+#ifdef CONFIG_BCM47XX_SSB
+static inline u32 __ssb_write32_masked(struct ssb_device *dev, u16 offset,
+				       u32 mask, u32 value)
 {
-	int irq;
-
-	if (ssb.chipco.dev)
-		irq = ssb_mips_irq(ssb.chipco.dev) + 2;
-	else if (ssb.extif.dev)
-		irq = ssb_mips_irq(ssb.extif.dev) + 2;
-	else return;
-	
-	if (enabled)
-		request_irq(irq, handler, SA_SHIRQ | SA_SAMPLE_RANDOM, "gpio", handler);
-	else
-		free_irq(irq, handler);
-
-	if (ssb.chipco.dev)
-		ssb_write32_masked(ssb.chipco.dev, SSB_CHIPCO_IRQMASK, SSB_CHIPCO_IRQ_GPIO, (enabled ? SSB_CHIPCO_IRQ_GPIO : 0));
+	value &= mask;
+	value |= ssb_read32(dev, offset) & ~mask;
+	ssb_write32(dev, offset, value);
+	return value;
 }
-
-#else
-
-#include <typedefs.h>
-#include <osl.h>
-#include <bcmdevs.h>
-#include <sbutils.h>
-#include <sbconfig.h>
-#include <sbchipc.h>
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
-#include <sbmips.h>
-#else
-#include <hndcpu.h>
 #endif
 
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
-#define sbh bcm947xx_sbh
-#define sbh_lock bcm947xx_sbh_lock
+#ifdef CONFIG_BCM47XX_BCMA
+static inline u32 __bcma_write32_masked(struct bcma_device *dev, u16 offset,
+				       u32 mask, u32 value)
+{
+	value &= mask;
+	value |= bcma_read32(dev, offset) & ~mask;
+	bcma_write32(dev, offset, value);
+	return value;
+}
 #endif
 
-extern void *sbh;
-extern spinlock_t sbh_lock;
-
-#define gpio_in()	sb_gpioin(sbh)
-#define gpio_out(mask, value) 	sb_gpioout(sbh, mask, ((value) & (mask)), GPIO_DRV_PRIORITY)
-#define gpio_outen(mask, value) 	sb_gpioouten(sbh, mask, value, GPIO_DRV_PRIORITY)
-#define gpio_control(mask, value) 	sb_gpiocontrol(sbh, mask, value, GPIO_DRV_PRIORITY)
-#define gpio_intmask(mask, value) 	sb_gpiointmask(sbh, mask, value, GPIO_DRV_PRIORITY)
-#define gpio_intpolarity(mask, value) 	sb_gpiointpolarity(sbh, mask, value, GPIO_DRV_PRIORITY)
-
-static void gpio_set_irqenable(int enabled, irqreturn_t (*handler)(int, void *, struct pt_regs *))
+static void gpio_set_irqenable(int enabled, irqreturn_t (*handler)(int, void *))
 {
-	unsigned int coreidx;
-	unsigned long flags;
-	chipcregs_t *cc;
 	int irq;
 
-	spin_lock_irqsave(sbh_lock, flags);
-	coreidx = sb_coreidx(sbh);
-
-	irq = sb_irq(sbh) + 2;
-	if (enabled)
-		request_irq(irq, handler, SA_SHIRQ | SA_SAMPLE_RANDOM, "gpio", handler);
-	else
+	irq = gpio_to_irq(0);
+	if (irq == -EINVAL) return;
+	
+	if (enabled) {
+		if (request_irq(irq, handler, IRQF_SHARED | IRQF_SAMPLE_RANDOM, "gpio", handler))
+			return;
+	} else {
 		free_irq(irq, handler);
+	}
 
-	if ((cc = sb_setcore(sbh, SB_CC, 0))) {
-		int intmask;
-
-		intmask = readl(&cc->intmask);
-		if (enabled)
-			intmask |= CI_GPIO;
-		else
-			intmask &= ~CI_GPIO;
-		writel(intmask, &cc->intmask);
+	switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
+	case BCM47XX_BUS_TYPE_SSB:
+		if (bcm47xx_bus.ssb.chipco.dev)
+			__ssb_write32_masked(bcm47xx_bus.ssb.chipco.dev, SSB_CHIPCO_IRQMASK, SSB_CHIPCO_IRQ_GPIO, (enabled ? SSB_CHIPCO_IRQ_GPIO : 0));
+#endif
+#ifdef CONFIG_BCM47XX_BCMA
+	case BCM47XX_BUS_TYPE_BCMA:
+		if (bcm47xx_bus.bcma.bus.drv_cc.core)
+			__bcma_write32_masked(bcm47xx_bus.bcma.bus.drv_cc.core, BCMA_CC_IRQMASK, BCMA_CC_IRQ_GPIO, (enabled ? BCMA_CC_IRQ_GPIO : 0));
+#endif
 	}
-	sb_setcoreidx(sbh, coreidx);
-	spin_unlock_irqrestore(sbh_lock, flags);
 }
 
-#endif /* BCMDRIVER */
-
 #define EXTIF_ADDR 0x1f000000
 #define EXTIF_UART (EXTIF_ADDR + 0x00800000)